Fast Ethernet local-area network switches are commonplace and can be purchased in 24- or 48-port configurations for less than $5 per port. Designing a Gigabit Ethernet LAN switch into similar port densities and form factors, however, is extremely difficult because of the power dissipation of physical-layer (PHY) components.
The 10/100/1000Base-T copper PHY is one of the most complex mixed-signal transceivers ever standardized for high-volume applications. To deliver full-duplex data of 1 Gbit/second over a copper unshielded twisted pair (UTP) cable rated only up to 100 MHz, each Gigabit Ethernet copper PHY must provide the equivalent of more than 250 million operations per second of digital signal processing (DSP).
Accomplishing this is a significant engineering feat requiring a careful blend of the two primary sections of the PHY: the DSP core and the analog front end (AFE), which is part of the physical media device interface. This complexity is borne out by the large gate count of a typical copper PHY: A 1000Base-T DSP core requires 750,000 to more than 1 million digital gates, and the AFE complexity is well above 250,000 transistors.
Because of the complexity of the signal-processing task, a 10/100/1000Base-T copper PHY is the dominant consumer of power in essentially all gigabit switch designs supporting copper media. First-generation 1000Base-T copper PHYs introduced in 1999 in 0.35-micron CMOS consumed well over 5 watts of power-too high for widespread use in high-density Gigabit Ethernet switch form factors. Subsequent generations of Gigabit Ethernet copper PHYs introduced through 2003 have approached 1 W per port, but these improvements have largely been achieved by reducing the power of the large digital section (the DSP core) of the PHY through the familiar power consumption benefits of reducing the supply voltage with newer, reduced-line-width CMOS process geometries.
The key to further power reductions beyond those allowed by finer process geometries is to examine the power dissipation of the line driver in the AFE. In fact, since the power dissipation of the DSP is substantially reduced in 0.13-micron technology and below, the AFE emerges as the dominant consumer of power in the 10/100/1000Base-T PHYs in production today.
The line driver
There are two basic architectural options for 1000Base-T line drivers: current-mode and voltage-mode (see figure).
The current-mode line driver consists of a single-ended current source-typically 40 milliamps-that pulls current from one side of the transformer or the other to generate the IEEE-specified five-level pulse-amplitude-modulated (PAM) signal for 1000Base-T.
The PAM-5 signal requires voltages of +1, +0.5, 0, -0.5 and -1 V at the load. Since the current source is high-impedance, the driver's output impedance is formed solely by the two 50-ohm termination resistors, which are in parallel to the 100-ohm load.
The current required (40 mA) for the current-mode line driver is high because the impedance seen by the current source is the termination impedance in parallel with the load impedance (100 ohms in parallel with 100 ohms = 50 ohms), and since the current is pulled to ground only, twice as much current is required to create the positive and negative voltages across the transformer through the magnetic coupling between the two halves of the primary. For example, to generate a +1-V symbol, the 40-mA current is steered all the way to one side of the transformer and is then steered all the way to the other side to generate a -1-V symbol. The current is split evenly between both sides for the 0-V symbol.
For a 2.5-V-based current-mode line driver, the average power dissipation per subchannel is: P(ave) = 2.5 V x 40 mA = 100 mW.
Since a 1000Base-T PHY consists of one line driver for each of the four twisted pairs, the theoretical power dissipation of the voltage-mode line driver is: P(current mode) = 400 mW per PHY.
As an alternative, the voltage-mode line driver takes a different approach and utilizes the commonly available 3.3-V supplies in switch designs. The differential outputs drive, with a low impedance, the five-level PAM voltages of +2, +1, 0, -1 and -2 V.
Since the reflected load impedance of the line is 100 ohms, the PAM voltages are divided down by a factor of two, thereby meeting the IEEE voltage template specification of +1-V peak seen at the load. However, in contrast to the current-mode design, the termination and load impedances in this case are in series, and the peak current driven from the voltage-mode line driver is, therefore:
I(pk) = 2 V / 200 ohms = 10 mA.
Further, the average current magnitude, assuming the five symbols are equally weighted, is: I(ave) = average of (10 mA, 5 mA, 0 mA, -5 mA, -10 mA) = 6 mA.
Thus, the theoretical average power dissipation of the voltage-mode line driver is: P(ave) = 3.3 V x 6 mA = approximately 20 mW (per channel).
Since a 1000Base-T PHY consists of one line driver for each of the four twisted pairs, the theoretical power dissipation of the voltage-mode line driver is: P(voltage mode) = 80 mW per PHY.
Because the 1000Base-T specification calls for pulse shaping that introduces other intermediate levels, and since the system is full-duplex and hence voltages are simultaneously being driven from the line driver at the far end, the actual numbers are slightly higher, that is, I(ave) = 6.43 mA, P(ave) = 21.2 mW and P(voltage mode) = 85 mW.
As designers can see, the current-mode line driver can be operated from a lower supply voltage (2.5 V) and is typically easier to implement. Its power dissipation is much higher than the voltage-mode driver's, however, because the required currents are more than six times as high: 40 mA, vs. 6 mA.
This difference arises principally because the impedance seen by the current source of the current-mode driver is the termination impedance in parallel with the load impedance (100 ohms in parallel with 100 ohms = 50 ohms), instead of in series (100 ohms +100 ohms = 200 ohms), as required by the voltage-mode driver, and because the current is pulled to ground only.
From this analysis, the theoretical power dissipation of the voltage-mode line driver is approximately one-fifth (80 mW vs. 400 mW) of the current-mode line driver. In practice, both line drivers dissipate additional power in bias currents and support circuitry, and since the current-mode line driver is simpler and does not usually require any op amps or other closed-loop circuitry, the voltage-mode line driver typically draws about 3x less power than the current-mode driver.
Therefore, since the line driver is the dominant, single source of power dissipation in most 1000Base-T PHYs, by using a voltage-mode line driver, a well-designed 10/100/1000Base-T transceiver can achieve less than 650 mW per port, which equates to a 300-mW savings over systems using a current-mode line driver design. This savings goes a long way toward meeting the 1-W-per-port target power budget for Gigabit Ethernet designs.
Nick van Bavel (email@example.com) is the vice president of technology, Phil Callahan (firstname.lastname@example.org) is the PHY product line manager and John Chiang (email@example.com) is the gigabit switch product line manager in Vitesse Semiconductor Corp.'s Ethernet Products Division (Camarillo, Calif.).
See related chart