MANHASSET, N.Y. Altera Corp. has unveiled what it claims to be industry's first FPGA-based, video-over-IP reference design.
Altera (San Jose, Calif.) developed the reference design using its Cyclone FPGA and the Nios II embedded processor. The reference design is intended to accelerate development of video-over-IP systems involving broadcast infrastructure as well as Ethernet-based data transport.
The Altera reference design can accept a configurable number of MPEG-2 transport streams and encapsulate the data for transmission over Ethernet. It can also regenerate a configurable number of transport streams using encapsulated data received from Ethernet.
"Altera's comprehensive, first-to-market video-over-IP solution provides us with a significant competitive advantage, and we have adopted it and their Ethernet-to-ASI solution for our next-generation digital head-end product," said Yu Zhi Wu, project manager of Pro Broadband Inc., in a statement.
The Altera reference design includes a hardware engine for performing user datagram protocol (UDP) and optional real-time transport protocol (RTP) encapsulation of the video data, thus allowing full Gigabit line rate to be achieved. The design also includes the Nios II processor and driver software for the industry-standard BSD IP stack running under the eCos real time operating system (RTOS).
Software running on the Nios II processor is used to manage the network connection, initiate multicast sessions and provide operational statistics. A web-based GUI is provided for user interaction.