Algorithmic synthesis helps hardware designers build and verify hardware more efficiently, giving them better control over optimization of their design architecture. The starting point of this flow is a subset of pure C++ that includes a bit-accurate class library. The code is analyzed, architecturally constrained, and scheduled to create synthesizeable HDL. Verification of this RTL is also an important part of the design process.
In a traditional design flow, crafting the hardware architecture and writing VHDL or Verilog for RTL synthesis requires considerable effort. The code must follow a synthesis standard, meet timing, implement the interface specification, and function correctly.
Given enough time, a design team is capable of meeting all these constraints. However, deadlines imposed by time to market pressures often force designers to compromise in area by re-using blocks and IP that are over-designed for their application.
Five years ago Mentor Graphics came up with rough criteria for making high-level synthesis compelling for real-world design. First, in order to justify the switch to a new flow, a designer needs to be able to build verified RTL an order of magnitude faster using high-level synthesis over manual methods.
So if a designer is currently building and verifying 1,000 gates per day, the same designer needs to be able to build and verify 10,000 gates per day to justify a methodology shift. Second, the design has to meet the same performance with no more than a 10% increase in area.
Why behavioral synthesis didn't work
Next we analyzed why behavioral synthesis had failed. Designers expected they could use wait statements to define their interface protocol. Unfortunately, a wait statement does not convey enough information to schedule a design without violating the interface protocol. There is nothing in the source language to prevent the time added by behavioral synthesis from breaking the interface protocol.
In an attempt to address this problem, new constraints were created to define interface timing, and the result was a synthesis language that fully defines interface timing. Unfortunately, interest in behavioral synthesis tools faded as designers realized wait statements could not be the only source of timing constraints. The wait statements in all behavioral languages, including SystemC, suffer from this drawback.
The timing constraints developed for behavioral synthesis, however, can be used for designs without putting timing or parallelism in the source. Removing timing and parallelism from the source language is what separates first-generation (behavioral) high-level synthesis from second-generation (algorithmic) high-level synthesis.
An algorithmic synthesis tool has a concise I/O timing constraint language that is separate from the functionality of the source. This allows the functionality and design timing to be developed and verified independently.
American National Standards Institute (ANSI) C++ is probably the most widely used design language in the world. It incorporates all the elements to model algorithms concisely, clearly and efficiently. A class library can then be used to model bit-accurate behavior. And C++ has many software design and debugging tools that can now be re-used for hardware design.
New system modeling languages such as SystemC or SystemVerilog can also be used, but this means teaching everyone a new language. The hierarchy and parallelism in these languages can be generated by a tool that synthesizes sequential C++ and that allows companies to take advantage of abstract system modeling without teaching every designer a new language. Designers are also able to quickly change the structure of the entire system without re-writing their source code.