Adding multiple processors to a system-on-chip may seem like an obvious way to boost performance, save power and leverage hardware acceleration where it's most needed. But multiprocessor SoCs raise design challenges that may not have obvious solutions.
On the software side, the challenge is partitioning the design and assigning tasks. On the hardware side, it's finding the right communications infrastructure and memory hierarchy to ensure high-bandwidth communications among processors, memories and peripherals.
"For most people, the biggest challenge of an MPSoC is, 'Where do I get my tasks to run?' " said John Goodacre, program manager for multiprocessing at ARM Ltd. "With large heterogeneous designs, you are asking the programmer to split up all the code and run it in the right place at the right time and not waste silicon."
"Heterogeneous MPSoCs are a solution to the design productivity challenge," Alain Arteri, director of engineering at STMicroelectronics, said in July during a keynote speech at the MPSoC Conference in Margaux, France. "But SoC design then becomes a memory hierarchy and bus design issue."
Many MPSoC designs today are heterogeneous. For example, a general-purpose CPU might be combined with a DSP or a video or graphics accelerator. An example is STMicroelectronics' Nomadik multimedia platform, which combines an ARM CPU with DSP subsystems and hardware accelerators.
There is, however, a trend toward MPSoCs that include multiple iterations of identical, general-purpose processing elements. These open the door to symmetric multiprocessing (SMP) and, arguably, a simpler software and hardware design challenge. The ARM11 MPCore, which includes up to four tightly coupled CPUs, provides a building block for an SMP approach.
Some heterogeneous approaches use multiple iterations of identical processors as well. IBM's Cell architecture, for example, includes one power processing element and eight identical synergistic processing elements. Cradle Technologies' multiprocessing DSP architecture comprises "quads" that include up to four general-purpose processing cores and up to eight DSP engines with their associated memory.
Behind all MPSoC strategies is a drive to higher levels of performance. For many designers, however, saving power may be an even stronger motivation. Using what ST's Arteri called "multiple noninterfering domains of intense activity," designers can turn on subsystems as needed and can offload tasks that would otherwise run on power-hungry CPUs.
But to take full advantage of such benefits, said Kourosh Amiri, director of marketing at Cradle Technologies, "system developers need an architecture that is designed with flexible application partitioning; intelligent resource sharing among the processing cores; and high bandwidth between the compute engines, memories and I/Os."