To illustrate, Figure 4 summarizes maximum compression requirements for three scenarios assuming an expected order magnitude increase in gate complexity, and assuming all current designs approach the limits of tester memory and tester clocking frequency. The darker shaded rows represent interim requirements during the technology transition period whereas the lighter shaded rows represent longer term requirements after newer testers have been fully deployed.
The first column describes the type of ATPG tests used for current designs: stuck-at only (SA) or stuck-at plus at-speed and bridging tests (designated DSM). The columns under Future Requirements designate the anticipated future type of ATPG tests; the factor increase in tester capabilities, in terms of memory capacity and clocking frequency; and the maximum required compression. In this example, newer testers will have double the memory and frequency of the older testers, though this is likely a conservative assumption.
Figure 4 Maximum required compression
In the first and second scenarios, designers plan to use the same types of ATPG testing, SA or DSM, respectively. The highest compression, 10x, is needed during each interim phase to compensate for the 10x increase in gate count expected before new testers are deployed. In the third scenario, pressures to improve test quality, as previously discussed, combine with future expectations to increase the maximum compression requirement to the range 10 x (4-to-6x) = 40-to-60x in the interim transition period.
Impact of nanometer processes
Nanometer processes (65nm and below) and ultra-high quality goals (DPPM < 100)="" place="" additional="" demands="" on="" dft="" methodologies="" to="" target="" ever="" more="" subtle="" physical="" defects.="" very="" high="" compression="" may="" be="" needed="" to="" meet="" these="" demands,="" though="" the="" compression="" requirements="" are="" closely="" linked="" with="" faults="" model="" types="" and="" atpg="" techniques.="">
Small delay defect testing offers the potential to detect subtle speed-related failures by deterministically targeting small delay faults starting from the longest paths in the circuit. This technique itself would produce more than an order magnitude increase in pattern count, all other factors being equal. However, the technology of small delay defect testing is still under investigation and is not supplied by any EDA vendor to date.
An alternative methodology, built-in self-test, also has the potential to meet the quality needs of nanometer processes without requiring high compression, though production solutions for self-test must be highly automated and non-intrusive to the design flows to minimize implementation costs and performance impact; otherwise companies do not benefit relative to other approaches.
As designs increase in complexity, semiconductor companies are seeking to lower their test costs even as they endeavor to achieve higher test quality. In response, designers have already begun to use scan compression techniques to reduce test execution costs, and are seeking more cost effective compression solutions that provide the largest return for investment in DFT resources nonrecurring engineering time and effort, recurring silicon overhead for compression, testers and software.
In most instances the benefits of scan compression are incremental above 95 percent TATR and TDVR. Firms may seek to reduce test application time further than this in very high volume manufacturing settings, or if they anticipate higher gate counts and transition gradually to more advanced testers. Very high compression solutions may be required to meet ultra-high-quality goals and test challenges related to nanometer processes, though the adjunct ATPG technology itself is still in development.
Built-in self-test represents an alternative approach that does not require high compression, but designers implementing self-test could be better served by more automated, and hence cost effective, solutions. An example is Adaptive Scan technology, a scan compression architecture developed at Synopsys that was designed to provide the benefits of test application time and test data volume reduction while minimizing impact on design flows and design performance.
1. S. Wei, P.K. Nag, R.D. Blanton, A. Gattiker and W. Maly, To DFT or Not to DFT? Proc. Of IEEE International Test Conference, 1997, pp. 557-566.
Chris Allsup is marketing manager for test automation products at Synopsys. He is a veteran in the EDA industry with over 20 years combined experience in IC design, field applications, sales and marketing.