Design variability is rapidly becoming the “norm” for electronics products. From packaging to logic functionality, electronic end products are expected to be more customized and configurable based on customer demand and field environment.
For logic design, this means the hardware must be able to handle a variety of functions, which leads to more devices and more real estate. A common method to handle this additional functionality has been to move them into switchable software modules handled by a microprocessor. However, a growing number of applications are relying on FPGA-based partial reconfiguration technology to leave logic functions in hardware, switch them in and out on demand all while leaving your core logic running.
An overview of partial reconfiguration
FPGA architecture allows design modules to be swapped on-the-fly. That’s nothing new, of course. FPGA reprogrammability has been helping engineers handle design demands for a number of years now.
But partial reconfiguration is different in that it allows a limited, predefined portion of an FPGA to be reconfigured while the remainder of the device continues to operate. This is especially valuable when devices operate in a mission-critical environment that cannot be disrupted while some subsystems are being redefined.
This powerful capability allows multiple design modules to time-share resources on a single device, even while the base design operates uninterrupted. Using partial reconfiguration, designers can dramatically increase the functionality of a single FPGA, allowing for fewer, smaller devices than would otherwise be needed.
Partial reconfiguration is useful for systems with multiple functions that can time-share the same FPGA device resources. In such systems, one section of the FPGA continues to operate while other sections of the FPGA are disabled and partially reconfigured to provide new functionality. This is analogous to an embedded design where a microprocessor manages context switching between software processes, except in the case of partial reconfiguration of an FPGA it’s the hardware, not the software that is being switched.
Partial reconfiguration provides an advantage over multiple full bit-streams in applications that require continuous operations that would not be accessible during full reconfiguration. One example, illustrated in Figure 1, is a graphics display that utilizes horizontal and vertical synchronization.
Because of the environment in which this application operates, signals from radio and video links need to be preserved but the format and data processing format require updates and changes during operation. With partial reconfiguration, the system can maintain these real-time links while other modules within the FPGA are changed on-the-fly. Important applications already using partial reconfiguration technology include reconfigurable communication and cryptographic systems.
Figure 1 Maintaining real-time links during partial reconfiguration
All user programmable features inside Xilinx Virtex or Spartan FPGAs are controlled by memory cells that are volatile and must be configured on power-up. These memory cells are known as the configuration memory and define the LUT equations, signal routing, IOB voltage standards, and all other aspects of the user design.
To program configuration memory, instructions for the configuration control logic and data for the configuration memory are provided in the form of a bitstream, which is delivered to the device through the JTAG, SelectMAP, Serial or ICAP configuration interface. As such, a programmed FPGA can be partially reconfigured using a partial bitstream. The partial bitstream can be used to change the structure of one part of the FPGA design while the remainder of the device continues to operate.