Another key addition is parametric models, which describe system properties and relationships. A new constraint block defines sets of parameters, along with expressions that show the relationship of one parameter value to another. Diagrams can be fed into a simulation engine and executed. "This allows us to establish any kind of constraint--voltage, gravity, drag coefficients--all the things engineers need to know about," said Low.
SysML also offers extensions that support the continuous flow of data, matter or energy, in addition to the discrete events supported by UML. SysML inherits from UML various ways of expressing concurrency, such as active objects, said Alan Moore, vice president of product strategy at Artisan Software.
Moore said the overlap between SysML and the UML 2.0 profile for SoCs has not yet been investigated. At STMicroelectronics, however, SysML's new features are attracting interest. Alberto Rosti, system design methodologies senior engineer, said that in principle, SysML should be even better suited for SoC modeling than UML 2.0.
"SysML is more tailored to the entire system," he said, "whereas UML is for modeling the software artifacts." ST sees SysML "as a platform-independent model for SoC design," Rosti said, that adds new capabilities for describing requirements and system properties, and possibly allows more accurate modeling of time.
IBM Corp. is using SysML to help customers model automotive systems, said Laurent Balmelli, research staff member at IBM's Tokyo research lab and a member of the SysML Team. He said SysML can model hardware and software architectures for the electronic control units that manage various automotive subsystems. Once the architecture is generated, engineers can run simulations and generate code for the entire system.
Balmelli emphasized that SysML does not replace implementation languages such as HDLs. Instead, he said, SysML comes into play when it's necessary to cross multiple domains with a single model--such as electrical, mechanical and software. Once you drill down into chip design, then you use a suitable implementation language. The details of the chip remain invisible to SysML, unless there's a parameter such as chip voltage that affects the rest of the system.
What's needed now, Balmelli said, is a more automated way to translate SysML models into implementation domains. "It's a very important subject of research," he said. "We want to know what transformation rules can bring your SysML diagram into a VHDL description."
Little EDA interest
Much of the interest in SysML today comes from the military/aerospace sector, but SysML should work for any type of system, Low said--including chips. "SoC is very adjacent to software, and execution is a critical component," he said. Tools like Telelogic's Rhapsody aren't just for graphical design, but can also execute and simulate SysML models, he said.
SysML is designed to work with two evolving interoperability standards: the OMG XMI 2.1 model interchange format and the ISO AP233 data interchange standard. Either of these, said Artisan's Moore, could transfer high-level design information expressed in a SysML modeling tool into a hardware design tool.
But will any such links be forged? As of now, the providers of SysML tools come from the embedded-software world. EDA vendors have shown little interest in UML or awareness of SysML. If SysML is going to bridge software hardware, it's up to interested companies like ST, IBM and Lockheed-Martin to do much of the construction.