In 1981 an industry leader was rumored to have said, "Nobody will ever need more than 640KB of RAM." Whether he said it or not might be up for debate, but it soon became abundantly clear that 640K would be never enough.
Amazingly, even after 25 years we aren't sure that memory requirements can be bound. Gigabyte memories, once the realm of science fiction, are taken for granted. Every new generation of consumer electronic gadget has applications that bedazzle the senses, greedily devouring more memory in the process. One can watch the latest video on a cell phone, take a picture with a pen and get the latest weather info on a wristwatch. Try doing that with 640KB of RAM!
As we push towards greater integration, current system-on-chip (SOC) designs dramatically increase memory content and show no signs of relenting. According to the Semiconductor Industry Association (SIA), memory already dominates over 60% of silicon area in SOC designs, and is projected to represent over 90% of the die area by end of the decade. New SOC designs are beginning to take on the appearance of a memory-chip with logic surrounding it.
The predominance of memory in SOC designs is made more acute by the variety of memory types that are being used today. The multi-functional nature of current designs is reflected by the International Technology Roadmap for Semiconductors (ITRS). Having an SOC design embedded with a DRAM along with a CAM, an EPROM, and a multi-port SRAM is not uncommon.
There can be several instances of the same memory that might exist on the chip with different architectures for high-performance, low-power, other form-factors, and so on. These variations require that, for design and analysis purposes, multiple instances of the same memory be treated as distinct entities.
Figure 1 2000 ITRS product technology trends
Source: ITRS 2005 Technology Roadmap
As we can observe, smaller device sizes have resulted in multiple advantages including greater functionality per chip, lower overall cost and higher portability, but they have also resulted in an ever-increasing set of design and manufacturing challenges. We shall restrict our discussion to issues that affect the simulation and verification of these embedded memory designs and some possible solutions.
From the literature, some of the key requirements of an ideal embedded memory from the designer's viewpoint can be summarized in the following table:
Table 1 Requirements of embedded memory
Consider a few of these requirements and their effect on current design methodology and designers.
Designing for high speed operation
Designing a fast read/write operation for nanometer memories requires consideration of several key issues, such as banking, power delivery, clocking speed, sense-amp sensing and timing, the wire loads on the bit lines, and the reference voltage and word-line driver strength, to name just a few.
In traditional sub-micron designs, pessimistic designers performed a critical-path analysis with a wire-load model with lumped parasitics that reflected the worst-case read/write scenario. While this provided an adequate lower-bound estimation of the design performance, a considerable amount of potential power savings and performance was wasted.
Given the coupling and interference issues, approaching nanometer embedded memory designs with lumped parasitics is unacceptable. Today's design flows utilize comprehensive load models with silicon-accurate parasitic values and simulating the designs as is, rather than abstract models of older flows.
Designing for low power consumption
Power measurement is a system-level activity requiring a comprehensive operational view of the module and the blocks that interact with it. Understanding power consumption in embedded memories requires a better understanding not only of the memory's V-I profile over combinations of read-write cycles, but also the power profile of the surrounding blocks that the memory interacts with.
Leakage power increases with lower geometries and is exacerbated with today's low-voltage transistor thresholds. It is therefore essential to consider all these elements in the memory along with the clocks and switching signals and be able to accurately simulate the entire design to estimate the power consumption.