A standard serial peripheral interface/Queued SPI/Microwire-compatible microcontroller communicates with its slave devices through a three- or four-wire serial interface. The typical interface includes an active-low chip-select signal (/CS), a serial clock (SCLK), a data input signal (DIN) and, occasionally, a data output signal (DOUT). Slave devices that are individually addressable, as is typical in I2C systems, communicate easily with a single microcontroller on a bus.
Many SPI devices are not individually addressable. Consequently, communication between those devices and a single microcontroller on a bus requires additional hardware or software organization. In a typical system in which one microcontroller communicates with multiple slave devices, the microcontroller uses one serial clock output (SCK) and one master-out/slave-in line (MOSI) to command all the slaves. The microcontroller allots an independent active-low slave-select signal (/SS) to each slave device so they can be addressed individually.
Because all slaves share the single clock and data lines, only the slaves with their /CS inputs asserted low will acknowledge and respond to the activity on the serial clock and data lines. This system is simple to implement when there are very few slave devices in the system. In systems with many slave devices, the microcontroller will need as many /SS outputs as the number of slaves. This approach increases hardware and layout complexity and becomes impractical as the number of slave devices increases.
An alternative method for serial-interface applications is daisychaining, which propagates commands through devices connected in series. In this configuration, a single /SS (or /CS) signal controls all the slaves' /CS inputs; all slaves receive the same clock signal. Only the first slave in the chain (Slave1) receives the command data directly from the microcontroller. Every other slave in the network receives its DIN data from the DOUT output of the preceding slave in the chain.
The slave must be able to input a command at DIN during a given command cycle (defined by the number of clock pulses required to clock in one command) and output the same command at DOUT during the subsequent command cycle. Stated simply, there is a DIN-to-DOUT delay of one command cycle. Moreover, the slave must only execute the command written to it on the rising edge of /CS. This means that as long as /CS remains low, the slave ignores the command and outputs it at DOUT on the following command cycle.
If /CS goes high after a given command cycle, all slaves execute the commands just written to their respective DIN inputs. If /CS goes high, data is not output at DOUT. This process makes it possible for every slave in the chain to execute a different command. As long as the daisychain requirements are satisfied, the microcontroller needs only three signals (/SS, SCK and MOSI) to control all the slaves in the network.
In a daisychained system, Slave1 receives data directly from the microcontroller. The data is clocked into the chip's internal shift register. As long as /CS (or /SS) remains low, this data propagates through to the chip's DOUT output. The DOUT of Slave1 connects to the DIN pin of Slave2, so the data is clocked into Slave2's internal shift register as the data appears on Slave1's DOUT output. Just as Slave2 receives its data from Slave1, the microcontroller can simultaneously send another command to Slave1. This new command overwrites the previous data in Slave1's shift register.
As long as /CS remains low, the data propagates through the entire daisychain until each of the slave devices has received its appropriate command. The command loaded into each slave's shift register executes on the rising edge of /CS.
Although there are many serial devices available, let's look at two examples of daisychaining using the MAX5233 (a dual 10-bit D/A converter) and the MAX5290 (a dual 12-bit D/A converter). In the first case, three MAX5233s are connected in a daisychain configuration. With the chip's reset value input (RSTV) pin connected to VDD, the analog outputs of the chip power up to midscale.