Large packets compensate for Ethernet's high overhead in LAN and WAN applications; limited flow control makes switches less complex throughout the network, and the ability to drop packets provides efficient congestion management. These characteristics, advantageous for LANs, can be devastating in chassis- and board-level control plane applications. Because control plane transactions are limited in size, high overhead reduces efficiency. For example, the TCP/IP header alone adds 40 bytes.
The RapidIO specification optimizes header size to maximize efficiency for packets typically used in control plane applications. The RapidIO protocol provides robust flow control and guaranteed delivery—both essential for maintaining the priority and reliability of control plane transactions—providing fabric usage in complex topologies in excess of 50 percent. Link-level error correction minimizes latency jitter, while minimizing or eliminating software stacks at endpoints substantially lowers end-to-end latency.
Implementing Ethernet to support control plane applications that are unable to tolerate packet loss requires significant over-provisioning, typically 25 to 35 percent, depending on a system's traffic demands. While over-provisioning reduces end-to-end latency and latency jitter, it decimates throughput: at 25 percent usage, the sustainable effective throughput of Layer 2 traffic for Gb Ethernet is about 250 Mbps and only 2.5 Gbps for 10 Gb Ethernet, depending upon average packet size.
Both Ethernet and RapidIO interconnect utilize the power efficiencies of a single-lane XAUI-like PHY interface, which dissipates anywhere from 70 to 200 mW at 3.125 Gbaud. For Ethernet applications using 1000Base-T PHYs, power dissipation rises to between 640 and 950 mW.
Ethernet protocol processing can consume more power compared to a RapidIO-based endpoint, because most Ethernet implementations run a software stack on a high-frequency host processor. Applying the rule of thumb that a Hz of CPU clock rate is required per bit of terminated TCP/IP performance, the power to terminate a line-rate Gigabit Ethernet link includes a GHz-class processor (adding on the order of watts of power) in addition to that consumed by the Gigabit PHY.