Scalable orthogonal frequency-division multiple access (OFDMA) is a key physical layer component associated with mobile WiMAX. It is an enabling technology for future broadband wireless protocols including 3GPP and 3GPP2 and their long-term evolution.
The underlying nature of OFDMA is ideal for an FPGA-based WiMAX basestation design PHY. By leveraging a scalable OFDMA engine, engineering teams can save up to 18 months of development time. FPGA building blocks include bit-level, OFDMA symbol-level and digital intermediate frequency processing blocks.
Symbol mapping and demapping are used in bit-level processing, as well as forward error correction (FEC) based on Reed-Solomon and Viterbi MegaCore functions. FEC schemes such as convolution turbo codes from third-party vendors can be used as well. OFDMA symbol-level processing includes subchannelization and de-subchannelization.
Fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) MegaCore functions support cyclic prefix insertion. Digital IF processing includes single- and multiple-antenna digital up converters (DUCs), digital down converters (DDCs), advanced crest factor reduction (CFR), and digital pre-distortion (DPD). The IF modem package allows easy and efficient multi-channel and time-multiplexed implementations.
Here, however, the focus is on PHY's scalable OFDMA engine and the implementation of OFDMA symbol-level processing algorithms. PHY is based on OFDMA modulation. Data are mapped in the frequency domain onto available carriers and converted to the time domain using an IFFT operation to convey the data across a radio channel. A cyclic prefix is added to the data's time domain representation to provide multi-path immunity and tolerance for synchronization errors.
Multiple OFDMA modulation modes are supported to accommodate variable channel bandwidths. This scalable architecture is achieved by using different FFT and IFFT sizes. Variable channel bandwidths ranging from 1.25 to 20 MHz are supported by 128, 512, 1K and 2K FFTs.
In this instance, FPGAs are well suited to FFT and IFFT processing because they are capable of high-speed, complex multiplications. Digital signal processors (DSPs) usually have up to eight dedicated multipliers; however, an advanced FPGA has 112 DSP blocks with 896 18 x 18 multipliers offering a throughput of nearly 500 giga multiply-accumulate operations (GMACs). This is an order of magnitude higher than that achievable with current DSPs.
The scalable OFDM engine consists of a transmit and receive OFDM kernel and transmit and receive subchannization. The OFDM kernel includes the IFFT and cyclic prefix insertion blocks in the downlink flow and the FFT and cyclic removal blocks in the uplink flow. To support OFDMA, an extension to the OFDM kernel is needed to allow each user to be allocated a portion of the available carriers. This process is called subchannelization.