Designers frequently turn to advanced power reduction techniques such as power shutoff (PSO) and multi-supply-voltage (MSV) architectures to help reach power consumption targets in advanced technology nodes (90 nanometers and below). Those techniques, however, can only be implemented if they are considered during the architecture phase of the design cycle. So it is important that power estimates be made early in the design project.
Here are five suggestions for estimating power early in a project, with minimal effort, while ensuring reasonable accuracy.
1. Determine your design's components of power consumption.
Early in the project, the design team should plot the components of power consumption. This estimate can be quite simple and perhaps can even be done using a spreadsheet before any RTL is complete.
The key here is to learn which components are fixed by specification and which can be affected through power reduction techniques. For example, I/O power is fixed by specification. Memory power may also be fixed by specification, but perhaps the memory can be powered down when not in use. If a large portion of the power is consumed by the clock, then the designer knows to focus on clock gating as a power reduction technique.
Estimating the ratio of leakage power to dynamic power for each component is also valuable so that the designers can select appropriate power reduction techniques. MSV and clock gating are effective in reducing dynamic power, while PSO is used to reduce leakage power.
When RTL becomes available, the designers can do an RTL power analysis even before the design is synthesized to technology gates. This analysis will not be as accurate as a gate-level analysis, but it will let the designer do a quick exploration to learn the potential power savings achieved with a given technique. For example, how much power could be saved if block X could be powered down 65 percent of the time, or if block Y operated at 0.8 volt rather than 1 V?
If the power analysis engine is integrated with the synthesis engine, the designer can also determine the effect of reduced voltage on design timing. The quick turnaround of RTL-based analysis lets the design team find the optimum power architecture early in the flow.
2. Use accurate switching- activity data.
Accurate data is critical for accurate power analysis. Obtaining it requires simulating test cases that accurately model real system stimulus. In many design flows, however, such simulation is not available until late in the design cycle, if at all.
To ensure an accurate power estimate, you need to use the most accurate data you have available at any given point in the design flow and revise your estimate as new data becomes available. Perhaps designers can extract data from system-level behavioral simulations or use simulation acceleration hardware to obtain useful data earlier in the project.
If switching activity data is not available from simulation, designers should estimate the switching activity on the chip's primary inputs and apply that estimate within the power analysis tool. Most power analysis tools can propagate the switching activity data through both the combinatorial and sequential logic. This is an excellent and often overlooked alternative to relying on the tool's defaults.
3. Consider simulation mode when generating switching activities.
Simulation mode is important to consider when generating switching activities. Many designers think switching activity generated from gate-level simulation will always yield more-accurate power estimation than activity generated from RTL simulation. This is not true. A zero-delay gate-level simulation will not account for any natural glitching that occurs in combinatorial logic, so it will always result in an optimistic power calculation. If the design team insists on gate-level simulation for power analysis, use an SDF-delay-based gate-level simulation.
4. Use accurate wire modeling.
Accurate wire modeling is essential for early power estimation. Every designer knows about the inaccuracies of wire load models when it comes to timing closure. Yet, many design teams use a "zero" wire load model for synthesis. This will result in inaccurate power estimation. Use a reasonable wire load model or, better yet, one of the "physical based" wire modeling technologies available in today's synthesis tools.
5. Use libraries that represent the worst-case power.
Synthesis is always done using worst-case timing libraries, but they do not represent the worst-case power. Dynamic power is usually the highest in fast conditions (high voltage, fast process, low temperature), which can be represented by the "best case" timing libraries. But leakage power typically increases with temperature. At 90 nm and below, when leakage is significant, it is wise to obtain a special library from your vendor that represents the worst-case dynamic and leakage power.
Designers must begin estimating power consumption early in a project. Accurately estimating power throughout the design flow will require significant designer effort, but the tips outlined here should help designers achieve their goals with efficiency and accuracy.
Brad Miller (email@example.com) is a senior technical leader at Cadence Design Systems in Ottawa.