The power architectures on today's power-cycled system-on-chip designs can be distressingly complex. Multiple power domains with many power modes require a thorough verification process.
Five technologies Power Definition Markup Language (PDML) specification, power-aware simulation, structural power checks, power-related assertions and formal analysis of the power control logic provide outstanding checking and coverage while shaving half the power verification time. These technologies are the key components of an effective power verification methodology to ensure that low-power design produces high-confidence chips.
In today's power-cycled systems-on-chip (SoCs), the power budget is lowered by reducing or shutting off power to regions of the device known as power domains. First-generation power-cycled SoC designs have only a few power domains, but newer designs now under development will feature as many as 20, producing numerous power modes.
This leads to exponential growth in the number of power-up and power-down transitions that must be verified before silicon is fabricated. Power-related bugs can be extremely serious, usually resulting in the need to turn the SoC.
PDMLs such as Common Power Format (CPF) provide a way to specify the power architecture of a design independently of the RTL (register transfer-level) description. The PDML specification includes the power/ground connectivity and control, the power shutoff behavior and interactions between different power domains. Many tools in the development flow can leverage the PDML file, so that the intended power architecture can be implemented correctly and verified both before and after the implementation. All of the power characteristics for the chip can be succinctly captured with PDML.
The second key technology is power-aware simulation, in which the RTL simulator reads and interprets the PDML so that power-up and power-down behavior can be modeled. A power-aware simulator can also perform checks to ensure proper response to power events, such as whether a power domain is powered down only after its outputs have been isolated.
Structural power checks can be performed as the power architecture is being modeled. Other checks must be performed during simulation, and these are best implemented using assertions, the fourth key technology. Many control functions and timing relationships specified in the PDML can be automatically transformed into assertions using a standard format such as SystemVerilog Assertions or Property Specification Language.
Monitoring these power-related assertions in simulation is critical to detecting errors in the power implementation, but it is possible that the set of tests will not exercise all important power behavior. Therefore, it's a good idea to supplement simulation with formal analysis, the final key technology for power verification. Formal analysis is exhaustive in nature, so it can find every bug related to the power assertions and, after the bugs are fixed, verify completely that none of the assertions can ever be violated.
Tom Anderson is a product marketing director at Cadence Design Systems. This article was co-authored by John Decker, architect, J. Marc Edwards, technical leader and Robert Juliano, senior technical lead at Cadence.