At 65/45 nm processing nodes, chip designers are being forced to juggle macro-level functional complexity issues (multiple operational modes), and micro-level process and manufacturing issues (multiple design corners), while trying to meet high performance and tight time-to-market targets. Low power and signal integrity issues (SI) exacerbate the physical design closure problem because an optimum result requires concurrent analysis of timing, power and SI interactions across all the different modes and corners, a process referred to as Multi-Corner--Multi-Mode (MCMM) design closure. The signoff requirements trend needs to consider an ever expanding set of corners for any given mode.
The incumbent place and route solutions in the market are at least 10-15 years old and were architected to address a different set of problems. Some of the challenges that need to be addressed at current process nodes were non-issues at that time. From a multiple corner and mode context, the critical handicap of the last-generation tools is the inability to handle more than two mode/corner scenarios at a given time. Specifically, the 'timing graph,' which is the most fundamental data structure in any implementation system, was generated from one mode and one setup/hold corner analysis. All place and route engines, including timing analysis, are hence limited by the information stored in this data structure. As it is very difficult to replace or retrofit this basic architectural limitation, it is nearly impossible for the traditional solutions to efficiently address the new multi-corner multi-mode design closure problems.
What is needed is the ability to capture the circuit behavior for any number of modes and corners dynamically and without impacting memory requirements and runtimes. In addition, all the place and route engines should concurrently analyze and optimize the various design metrics including timing, power, and SI across all modes and corners. The solution should scale efficiently for increasing design sizes and the high number of mode/corner combinations.
Designers have been addressing the new design closure problem by painful constraint merges, guessing design margins, and using worst-case corner conditions during the early phase of design implementation. During the later phases of the design cycle, these last-generation implementation flows force designers to manually analyze and fix the effects of all other design and process variation combinations in an iterative and non-convergent process. This is a very expensive and unpredictable process that frequently leads to missed schedules or reduced chip performance.
Low power and signal integrity related flow issues add to the design closure problem due to increasing number of modes and corners.
SI is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches, and unexpected signal delays. Customers designing at 65 nm and 45 nm are experiencing a significant increase in SI-related timing violations due to increasing dominance of lateral wire capacitance. The problem is exacerbated by an explosion in the number of mode/corner scenarios that must be addressed, significantly increasing the time to design closure. Current solutions are severely limited due to inability of the core timing engines to represent more than one early and one late corners for timing window calculations. This severely hampers design teams who are forced to run multiple, corner specific extraction and timing analysis runs for delta delay and glitch analysis separately. The results are then analyzed followed by a manual, iterative, and non convergent process to close the design. Obviously, this approach is slow and error prone, and cannot really result in an optimized design, because the interactions across modes and corners are not considered simultaneously.
What is needed is a built-in MCMM static timing analysis engine that concurrently computes delay shift and glitch for any number of modes and corners automatically in a single pass. MCMM-SI analysis lets you address reliability issues such as crosstalk delay, glitch, power and electromigration while reducing the time to achieve design closure. In addition, detailed routing and optimization engines also need to address SI violations concurrently over all variation scenarios.
The traditional place and route solutions are no longer adequate for reaching design closure on timing, SI, and power constraints within tight design schedules because they cannot address multiple modes and corners concurrently during place and route. We need an architecture that can comprehensively address the variability problem throughout the design flow. We need a solution that removes the unpredictability from the physical implementation process. It should help designers to stay on schedule and meet their market windows, while tackling the advanced design challenges of 45 nm and below.
An effective place and route solution delivers a comprehensive set of capabilities to help designers close timing, power, and SI across any number of modes and corners. Some of the innovations required include:
* A new timing analysis architecture that can concurrently address multiple modes and corners
* A variability-aware routing approach that optimizes for OPC, CAA and other DFM metrics during place and route
* Flexible tool architecture and power reduction technologies for the full spectrum of low power design styles
* A scalable data model that can represent 100+ million gate designs in hierarchical/flat design methodologies
Sudhakar Jilla is the marketing director at Mentor Graphics. Over the past 15 years, he has held various application engineering, marketing, and management roles in the EDA industry. He holds a Bachelors degree in Electronics and Communications from University of Mysore, a Master's degree in Electrical Engineering from the University of Hawaii, and a MBA from the Leavey School of Business, Santa Clara University.