Rather, the best way to approach the problem of unroutable designs is to reduce the possibility of severe congestion by examining ways to create a better starting point for physical implementation. This can be done early in the synthesis phase of design, prior to netlist handoff. There are two distinct elements of this approach: prediction and mitigation. Used separately or in tandem, their goal is to prevent severe congestion from occurring in the first place (and to do so as early in the design flow as possible).
Prediction is the ability to discover whether routing congestion will occur once a design is physically implemented, and to identify the causes and severity of the congestion. Physicist Niels Bohr once said that "prediction is very difficult, especially about the future"; but when it comes to predicting congestion, the task has been simplified by advances in synthesis technology. For example, Synopsys' Design Compiler Graphical synthesis product models the demand and capacity of global routing using technology shared across the company's synthesis and physical implementation tools. After running synthesis, the user can access a report assessing congestion in the synthesized netlist:
Overflow = 4651
Max = 5 (10 GRCs)
GRCs = 3401 (0.59 percent).
The virtual router in the synthesis engine reports that 3,401, or 0.59 percent, of 576,440 global routing cells (GRCs; i.e., grids) contain an "overflow" of 4,651 congestion violations. A maximum of five violations per cell occurs in 10 of these grids. Similar statistics are given for violations and overflow in horizontal and vertical directions.
This report lets you know whether you have a routing problem, but because pinpointing the underlying causes requires more details about the congestion hot spots, a graphical layout viewer provides interactive visualization. Congestion maps (contour maps color-coded by each grid's congestion severity level) can help you discover whether the hot spots are related to physical and floor-plan constraints (affecting port locations, channel depth, macros, keep-outs and so on) or RTL logic structures (affecting cell connectivity). The viewer also lets users identify the standard cells contributing to the congestion.
At this stage, you have to make an informed decision about what to do next. You might have to alter the floor plan based on your early prediction of the congestion hot spots. Or, the revelation that certain logic cells are contributing to congestion might require revision of the RTL itself. Unfortunately, massaging your source code to improve wire routability in the synthesized netlist can be an arduous chore.
However, using the congestion command line switch in Design Compiler Graphical allows a netlist with less congestion to be generated automatically during synthesis. This command performs standard logic cell optimizations that reduce the incidence of highly interconnected cell topologies.
Consider the case of large buses fanning into N:1 multiplexers in a block. The multiplexer cells have a high fan-in that could lead to severe congestion, so the synthesis tool analyzes the design and maps the high-fan-in multiplexers in the congested block to multiple low-fan-in equivalents. This way, the interconnect is distributed more evenly across grids in the affected block. Synthesis optimization thus reduces violations per grid and mitigates routing problems in a region of the design that would have been a congestion hot spot.
Chris Allsup (firstname.lastname@example.org) is marketing manager in Synopsys'
synthesis and test marketing group. A member of the IEEE Computer Society, Allsup has authored numerous papers and articles.