SAN JOSE, Calif. The HyperTransport Consortium is giving a speed boost both to its chip-to-chip interconnect as well as a board-to-board version that has yet to gain market traction. The news comes at a time when the PCI Special Interest Group is in the middle of its next big leap, the definition of a PCI Express 3.0 standard.
The PCI SIG has provided details about an update of its current PCI Express 2.0 standard due early next year. Chip makers are beginning to roll out second-generation parts for Express 2.0, including a set of switches with built in direct memory access announced by PLX Technology.
Advanced Micro Devices is the lead developer for HyperTransport, primarily used as an integrated chip interconnect on its processors. PCI Express has a much wider following because it is used in both Intel and AMD PCs and is gaining traction in embedded markets.
HyperTransport version 3.1, announced Monday (Aug. 18), handles up to 6.4 GigaTransfers/second at rates up to 3.2 GHz, up from 2.6 GHz. It delivers maximum theoretical throughput of 25.6 Gbytes/s on a 16-bit link, about a 23 percent increase over the 3.0 version released in 2006.
By contrast, the existing Express 2.0 spec runs at up to 5 GT/s and can deliver 16 Gbytes/s aggregate on a 16-channel link. The 3.0 version, set for release in late 2009, will handle up to 8GT/s and deliver up to 32 Gbytes/s.
The HyperTransport group is not commenting on any work on its next major revision beyond the version 3.1 midlife kicker. It is still characterizing the latency of version 3.1, typically a strong point for the technology.
Overall, version 3.1 "is not a dramatic increase in performance, but that is in response to the market that asked for a balanced design with more performance and manageable power consumption," said Mario Cavalli, general manager of the HyperTransport Consortium.
The interconnect uses new scrambling, training and retry mechanisms as well as enhanced cyclic redundancy checking. "We have eaten into some of the margin in our electrical specs to maintain trace length, and there will be a slight increase in power consumption" that the group has not yet not characterized, said Jeff Underhill, a HyperTransport member from AMD.
Separately the group has upgraded its HTX specification for board-to-board links to the version 3.0 data rates. "We didn't want to push the connectors to the full 3.1 speed because we wanted to avoid the capacitance it would create on the traces," said Underhill.
The faster spec aims to enable FPGA-based co-processor boards. "Our recently announced Stratix IV family of FPGAs was designed from the start to support HT 3.0 and will enable strong performance for HTX3 board designs," said Misha Burich, senior vice president of research and development at Altera, speaking in a press statement.
To date, only four boards of any kind have been announced using the HTX link introduced in late 2004 and two of them are no longer on the market, said Cavalli.
"As a niche within a niche, HTX is not going to have volumes or breadth of mainstream boards to rival PCI Express," said Jag Bolaria, a senior analyst with The Linley Group (Mountain View, Calif.). "With increasing performance and features for Express as well as its momentum, it's challenging for HTX to maintain a long term sustainable position," he added.
Other analysts noted that as much as 98 percent of the use for the HyperTransport chip interconnect is tied to AMD server CPUs. "I have seen very little use of HyperTransport beyond that application, except for some Cisco Systems ASICs a few years ago," said Steve Berry, president of Electronic Trend Publications (Campbell, Calif.).