Canmore is Intel's most complex system-on-chip design to be released to date. The company has been on a path of growing its SoC capabilities for some time, forming last year a corporate SoC enablement group under Gadi Singer, former head of EDA at the chip giant.
Intel has considered it part of its technology strategy to develop common SoC flows and intellectual property libraries. In the wake of the dotcom bust, Intel has divested interests in communications to focus its energies on pushing its x86 core into everything from sub-2W mobile devices to graphics and parallel supercomputers with its upcoming Larrabee chip.
"They are doing exactly the right thing, pushing the x86 everywhere," said Fred Weber, former chief technology officer of archrival Advanced Micro Devices who now heads a memory chip startup. "This is the sort of thing I have been preaching for years," said Weber on hand for one IDF session.
The Canmore designers got most of the IP blocks and tools they needed from various Intel divisions, including the new SoC group, said Suri Medapati, principal engineer and architect in Intel's digital home group who led the design effort.
Most of the IP on Canmore comes from Intel's chip set and mobile groups. The processor is the 800 MHz Dothan core from Centrino notebooks, and the graphics is an Imagination Technologies core supporting OpenGL ES 2.0 also used by the mobile group. The chip set group provided cores for 2.5 GHz PCI Express, serial ATA 2.0, USB 2.0 and a gigabit Ethernet MAC.
A decode block started with technology acquired about three years ago with Israeli startup O-Plus. Intel upgraded that core for a previous part and enhanced it again for Canmore. It now handles MPEG2 and H.264 decode for up to two simultaneous 1080i streams at 60 frames/second. A dual 300 MHz audio DSPs came from Tensilica.
Two other blocks were homegrown by the Canmore team--a display processor for scaling and interlacing and a security processor. The latter block handles conditional access keys for cable-TV card security and accelerates AES, 3DES, RSA and other algorithms.
The chip also includes three 800 MHz DDR2 controllers, six 10-bit video DACs and support for HDMI 1.3a.
The Canmore group created its own 90nm EDA chip design flow using a combination of tools it designed itself, ones from other Intel groups and third party tools. It uses some parts of a standard SoC flow created by the corporate team under Singer.
The digital home team has already finished a 45nm design flow for its next-generation parts which are well along in design. It has also helped the corporate SoC group in an effort to define an Intel standard SoC bus yet to be announced.