SAN FRANCISOThere is no single solution for effective low-power semiconductor design, which requires the collaborative efforts of chip designers and EDA vendors and is increasingly focusing on the register transfer level (RTL), according to Vic Kulkarni, president and CEO of Sequence Design Inc.
Over the past eight months, designers are increasingly implementing power management techniques in RTL, where almost 80 percent of total power savings can be realized, Kulkarni, said.
"One can do a lot of 'what if analysis' at the RTL phase, before it's submitted to synthesis," said Kulkarni.
Through analysis alongside customers, Sequence has identified 22 different techniques for reducing static and dynamic power consumption from the electronic system level (ESL) to RTL to the gate level, Kulkarni said.
Of the 22 techniques, Kulkarni said, Sequence products can address six or seven. "There is no silver bullet," Kulkarni said. "No one company can solve all the challenges [associated with power management]."
On Wednesday (Sept. 10), Sequence issued an announcement to tout the role of its PowerTheater design tools in the recent tape out of a mobile processor by fabless chip company NemoChips Inc. According to Sequence, the combination of low-power design techniques and PowerTheater enabled NemoChips (Fremont, Calif.) to achieve a 52 percent reduction in total power compared with previous generations of its product.
The processor, co-designed by Faraday Technology Corp.'s SoCompiler Design Services, is designed for mobile computing with streaming high-definition video and draws significantly less power than competitive products, according to the companies.
Kulkarni touted NemoChips' accomplishment as an example of the type of collaboration needed for low-power design in an era when battery life for mobile consumer products has become an important competitive differentiator.
" One tool company cannot solve [the problem]," Kulkarni said. "It really needs to be a partnership with design centers and end customers."