3D semiconductor packages enable the form and function for many devices we use in our daily lives--mobile handsets, personal entertainment devices and flash drives, to name a few. For people who rely on such implantable medical devices as insulin pumps or defibrillators, these 3D packages play a critical role in improving quality of life. Functional density, weight and configurability are just a few of many reasons a growing number of semiconductor products are going vertical using stacked-die, package-on-package (PoP) or through-silicon-via (TSV) packages. Each method provides unique benefits. However, targeted design planning, implementation and analysis strategies are required to achieve the full potential of these approaches.
|3D semiconductor packages need targeted design planning and analysis strategies to achieve full potential|
PoP is one of the fastest-growing packaging formats, with a 40 percent compound annual growth rate projected through 2012, according to TechSearch International. The ability to test at the package level and ease of multisourcing make PoP a popular choice with OEMs, but PoP necessitates careful coordination and design planning. A typical PoP includes a large digital device in the base package and some form of memory in the top package. It's likely the memory is a standard catalog device with fixed pin assignments, so there's not a lot of flexibility with its package layout. Therefore, one important design aspect is coordinating the pad interface between the top and bottom packages. This becomes a significant design challenge when multiple memory sources--each with the potential for different pin assignments--are factored in.
The key to efficient PoP devices is to plan the design when options to effect change are greatest. PoP planning should take place prior to, or concurrent with, chip floor planning, because of the direct relationship between the I/O pad-ring layout and package-to-package interface pads. Ideally, the interface becomes the starting point for design planning; the memory devices dictate pad placement, and the I/O pad-ring placement is modified as necessary. The die-attach method also figures into planning, as the configuration of bond fingers for wirebond and the bump pattern for flip-chip behave as intermediate connection points between the package interface pads and the I/O pad ring. Other planning considerations include the routeability of the bottom package, net name differences, and even the host printed circuit board (PCB). The objective is an I/O pad-ring layout that meets the connectivity needs of the core logic and results in the most cost-efficient package layout possible--i.e., the fewest number of layers and vias, and the shortest trace length.
This type of coordinated design planning across the chip, multiple packages and, in some cases, the PCB, can be challenging and frustrating--especially with conventional methodologies developed for sequential design flows that use separate tools and databases for packages and chips. Therefore, design teams often collaborate, using spreadsheets to communicate pad assignments. The shortcoming of this approach is that it's based on snapshots of static data, resulting in a highly iterative, error-prone process that does little to reduce cycle time or cost of results.
A new generation of EDA tools, such as Sigrity's OrbitIO Planner, takes a revolutionary approach to concurrent design planning and feasibility by bringing all data sources together into a common, unified planning environment. Functionality for wirebond and route feasibility provides the means to evaluate design aspects traditionally associated with detailed implementation while the design is still in the planning stage. This approach facilitates pad placement, and derives and evaluates connectivity scenarios in the context of the entire system. A unified chip-package-board data model automatically propagates changes to adjacent domains, providing instantaneous feedback on their system-wide impact. Optimizing the I/O pad ring and package-to-package connectivity for performance, cost and manufacturability prior to detailed implementation results in timely, efficient PoP development.