Battery-powered devices are coming out in large volumes from 65nm
manufacturing. This advanced process technology enables devices to
leverage significant benefits beyond those of their predecessors.
Devices fabricated using 65nm allow designers to integrate more
transistors on a single die. They also support inclusion of multiple
intellectual property (IP) cores, more embedded memories, and more
complex analog circuitry while offering higher performance, lower power
consumption and greater cost savings than similar devices manufactured
However, transistor leakage current in devices manufactured in 65nm
is exponentially higher than that observed in previous nodes. Hence,
large foundries such as TSMC have made leakage reduction a priority at
the 65nm reference flow.
Leakage is not a new phenomenon, but at 65nm, operating voltages
are lower than before, and it follows that the threshold voltage (Vt)
to turn on a transistor is also lower. The lower threshold voltage
often triggers inactive conditions, causing significant source-drain
current flow or leakage.
The latest circuit design techniques to combat this condition often
deploy multithreshold logic gates with a high-Vt header or footer built
into the logic gate itself, turning it off during idle mode.
Specific power shut off modes are also included within the design
logic, and designers are using more gated clocks to manage power for
each clock domain in the design.
To benefit from these new techniques, engineers must pay
significant attention to power consumption throughout the entire design
flow. Both hardware and embedded software engineers must be involved in
the process early on for a successful, on-time product release.
Low-power design also impacts verification, specifically the
validation of all power-management features. This requires extensive
verification under all possible operational conditions, including tests
of each power mode.
Verification of all power modes—power-up or -down— and their
accompanying sequences must be done before tape-out. Verification
engineers must also include tests to ensure that the functionality of
isolation logic is working. This is done using extensive test suites
with both random and directed cases.
Achieving robust verification of these power-specific features is
not a trivial effort and also requires significant attention throughout
the design flow. For example, low-power logic test suites must ensure
that specialized logic reduces dynamic power and guarantees that the
powered-off circuitry does not propagate random data to active
circuitry in all operating conditions.
To ensure that these conditions do not happen, verification
engineers must use a significant amount of simulation and other formal
verification resources at every code change during design.
One area often overlooked, or at best considered late in the design
cycle, is a device's power consumption during manufacturing test. There
are numerous concerns related to design-for-test (DFT),
specifically for low-power devices.
Early and thorough attention to power consumption during
manufacturing test is essential to ship reliable low-power devices in
volume. Significantly exceeding the devices' power specification during
manufacturing test can lead to gate-oxide breakdown at best, and can
destroy the chip at the worst.
The most optimal solution for low-power DFT involves the adoption
of a design-with-test (DWT) flow to best drive test issues within the
standard design and implementation flows, and consequently ensure its
minimal impact on and the delivery of high-quality low-power devices.
A DWT methodology encompasses a common power-aware test strategy
throughout the entire flow, enabling individual tools to minimize the
impact of low-power test at each step in the flow and thus meet the
test challenges of 65nm low-power manufacturing.
DWT provides a deep integration of power concerns among design,
implementation and test tools. This enables global optimization of
power limitations with other constraints such as timing, area, yield
Enabling low-power DFT
In the case of DWT, the deep integration of tools and their smooth
interoperability account for power constraints among RTL verification,
synthesis, test, equivalence checking, floorplanning, and placement and
The resulting global optimizations produce highly testable silicon
that meets its power budget during functional operation and testing in
the manufacturing flow. This approach requires tools within the flow to
have a common understanding of a device's power requirements by using a
common file to specify power issues as the design progresses through
High-quality low-power devices require significant DFT throughout.
DFT must be expanded, and its logic must control and test power-related
circuitry within the limits of the power specification during
manufacturing testing (wafer sort, package testing and environmental
In particular, a low-power design that leverages DWT will allow for
easy insertion of power-aware DFT structures, enabling the testing of
individual power domains within the overall power budget.
Devices often have voltage islands dispersed on the die, which must
be turned on/off with data scanned into the power control signals
during manufacturing test.
Accounting for these multiple voltage islands in a device often
leads to excessive power consumption during manufacturing test. The
challenges of low-power test do not stop with controlling power
consumption during testing.
To achieve high quality in low-power environment isolation cells,
level shifters and state retention registers must be controllable
through a scan chain if they are to be tested. This control enables
testing of these complex structures to ensure that random, systematic
or even subtle low-power specific defects can be found.
In a DWT flow during physical implementation test insertion, the actual
connection of scan chains to the boundary scan I/O, embedded
memory BIST controllers,
on-chip compression logic, on-product clock generation and IEEE 1500 wrappers is always
done considering power consumption.
For example, when on-chip test compression logic is connected, it
has a significant bearing on power consumption. Note that power
trade-offs must be made during the insertion of this on-chip
Creating the optimal scan- chain length demands a full
understanding of power considerations. This is to ensure that power
consumption during shifting of the large number of short scan chains
associated with on-chip compression will not negatively affect power
Due to growing concern over power consumption during test,
automatic test pattern generation
(ATPG) now plays a key role in the creation of
power-optimized test patterns. This is done by limiting switching
activity and leveraging power-management logic to limit power.
For example, power-aware ATPG reduces excessive power consumption
by intelligently filling "don't-care" bits in the scan chains so that
flip-flop switching is kept to a minimum.
Finally, DWT keeps production costs down by ensuring the success of
tests run for first time on the tester. This is achieved by the tight
integration that DWT provides between test and power verification. A
robust verification— using technologies such as simulation, equivalence
checking, constraint generation, advanced formal analysis—of
manufacturing tests prior to chip tape-out enables first-time success
for ATE programs.
The best way to ensure successful manufacturing test in a low-power
environment is through upfront consideration of power consumption
during test with power-aware DFT and ATPG tools. For these tools to be
most effective, tests must be made part of the design process.
With tools deeply integrated and power consumption highly
considered, DWT will no doubt spell continued success for low-power
Tom Jackson is Product Marketing
Director at Cadence Design Systems.