There is a clear move in the communication sector to improve overall I/O performance. Line speeds are already in the 10-Gbit/s range and higher density line cards are being enabled by advances in semiconductor and optical technology.. Thus, designers need increased bandwidth interconnects that will reduce pin counts for the movement of data between chips and across backplanes.
Recognizing the industry's need for the entire component level infrastructure to be upgraded to support higher system capacity, the Optical Internetworking Forum (OIF) started the Common Electrical I/O (CEI) project. The goal of CEI is to define electrical specifications for 4.976 to 6+ Gbit/s and 9.95 to 11+ Gbit/s serial signaling for chip-to-chip and board-to-board applications. These specifications will provide the basis for the electrical interfaces being used, enabling higher capacities needed for the next generation of systems. Let's take a look inside the CEI project and examine what impact this project will have on communications system designs.
The Physical and Link Layer (PLL) Working Group of the OIF specifies implementation agreements (IA) that enhance the interoperability of communication links at the optical level as well as at the electrical interface, including the electrical interface definition includes both signal properties and protocol between the different components in a typical optical networking application. Figure 1 provides an architectural overview of the various components and interfaces that have been defined by the OIF PLL group.
Figure 1: Diagram illustrating the key O/I electrical interfaces
The Serdes Framer Interface (SFI) defines an electrical interface between Sonet/SDH framers and high-speed parallel-to-serial/serial-to-parallel (serdes) logic. The serdes logic typically resides inside the optical module that will carry data traffic; however, it can also be placed on the host application board.
The System Packet Interface (SPI) sits in between the physical layer (PHY) device and the rest of the Sonet/SDH System (i.e. between the Sonet/SDH framer and a link-layer device). SXI-5 is a common electrical specification that defines the electrical I/O characteristics for 2.5-Gbit/s lanes used by OC-768 SPI-5 and SFI-5 interfaces.
The TDM Fabric-to-Framer Interface (TFI-5) IA is an alternative framer interface to SPI-5. TFI-5 is targeted for packet/cell switch fabrics and operates at the STS-48/STM-16 equivalent bit rate over a backplane.
The challenge when designing a system is to maximize its capacity while minimizing size, power, and implementation costs. Thus, one of the key factors driving the system's entire internal infrastructure is its I/O capacity, which is the product of the number of cards in a system and the capacity per card. This makes the physical size of an I/O module and its capacity a significant issue to the system architect. Recent advances to reduce power consumption and package size, while increasing signaling speed in fiber optic transceivers are helping to drive up the capacity per card. Advances in packaging and electrical signaling are also necessary to reduce the systems overall size.
Recognizing the industry's need for the component level infrastructure to be upgraded in support of higher system capacity, the OIF authorized the PLL Working Group to begin the CEI project. Each of the rates defined by the CEI project will support both short reach (SR; 0 to 200 mm or 8 inches of printed circuit board trace with up to one connector) and long reach (LR; 0 to 1 meter or 39 inches of printed circuit board trace with up to two connectors) applications.
I/O Capacity Explosion
An example of an application that will make use of the CEI 10-Gbit/s SR specification is the recently, introduced XFP 10-Gigabit small-form-factor pluggable (SFP) optical module. This package definition was completed by the XFP Multi Source Agreement (MSA) Group (www.xfpmsa.org). By using a serial high-speed interface and reducing the necessary number of signal pins, the group was able to reduce the overall width of the package, as demonstrated in Figure 2.
Figure 2: Diagram showing a typical XFP module and the SFP XFP module.
Figure 3 provides a comparison of the physical dimensions of various modules, which demonstrates that the XFP has the smallest footprint of competitive 10-Gbit serial solutions currently on the market.
Figure 3: Comparison of 10-Gbit module footprints. (Source Ignis Optics)
Figure 4 demonstrates the impact of the serial line rate on the number of electrical pairs that would be needed at the switch card as the optical capacity of 16 line cards feeding into the switch card is varied from 20 to 320 Gbit/s. It is clear that the I/O capacities enabled by the reduction of the XFP module in packaging size is providing a catalyst to the industry to upgrade the entire underlying infrastructure used to develop current systems.
Figure 4: Impact of serial line rates on the number of electrical pairs required in a design.
Looking into the CEI Project
CEI SR signaling will provide the basis for the next generations of SFI and SPI interfaces, while CEI LR buffers will power backplane communications and next generation TFI interfaces. Four separate clauses will define these four specifications; namely, 6G+ SR, 6G+ LR, 11G+ SR, and 11G+ LR, respectively. The SR and LR specs will endeavor to use common specifications at 6G+ and common specifications at 11G+ as much as possible.
CEI buffers will be based on high-speed, low-voltage logic with a nominal differential impedance of 100 ohms. Connections are point-to-point balanced differential pairs and signaling is unidirectional.
The CEI project specifically excludes any requirements on pin-out, management interface, power-supply specification, or higher-level activity such as addressing or error control. Signaling is DC balanced non-return-to-zero (NRZ) with appropriate sync or framing bits provided by respective protocols.
OK, now that we've laid out some of the basics, let's look in more detail at the CEI SR and LR specs. We'll start with the SR efforts.
CEI SR I/O
The new CEI signaling interfaces will enable the reduction in bus widths required to support higher capacity line cards by reducing board real estate requirements and reducing power requirements to further simplify line card design. tThe development of the 10 Gigabit Serial Electrical Interface (XFI) by the XFP MSA group has enabled serial 10-Gbit/s transmission over 8-in. of FR-4 with one connector. It can easily be seen how chip-to-chip applications, such as SFI and SPI, could be taken to new levels of performance by CEI SR buffers similar to XFI. But, to be a truly'common' electrical specification, the SR spec needs to tackle the following technical issues:
- Data coding requirements: Different protocols and applications may required different encoding techniques. These encoding methods can affect the jitter introduced by the channel and the phase-locked loop filter characteristics. The CEI project analyzed the impact of the different coding schemes to maintain support of the broadest range of standard interfaces. The correct determination of the coding effects on electrical and jitter characteristics is vital to guaranteeing interoperability.
- Signal levels: Signal levels are minimized to reduce power and emissions. However, the levels still allow for sufficient signal to noise ratio to make the channel operate at a low bit error rate (BER). The ability to DC couple was also considered for direct chip-to-chip connections.
- BER requirements: The industry desires lower BERs than the normal optical BERs of 10-12 for the underlying infrastructure in order to maintain the 10-12 BER for the overall system.
- ESD: Electrostatic discharge (ESD) protection must be provided up to the maximum level while avoiding the degradation of the signal integrity.
- Channel characteristics The correct definition and modeling of the channel characteristics will allow vendors to avoid "over-designing" the interface to accommodate for unknown variances in impedance and return loss.
- Jitter requirements: The jitter requirements of even this relatively short distance link need to be carefully specified in order to avoid impacting the optical jitter requirements and avoid over-designing of either the transmit or receive interface.
- Constraints on optical channel specifications: The solution selected should not impact the optical channel requirements. This will allow the widest use of the interface specification.
CEI LR I/O
The CEI LR buffers will power backplane communications and next-generation TFI interfaces. System vendors will use these buffers to not only create new systems, but to also extend the life of existing systems by expanding the backplance capacity of such systems.
Legacy backplanes pose a particularly challenging problem, since there is a limited ability to improve system performance because of a fixed electrical channel. The CEI 6G+ LR buffers will enable the existing and upgraded backplanes to achieve higher capacities. In a backplane environment the capability of every high-speed pair on each signal layer needs to be considered, especially given the various layers within the backplane. Figure 5 demonstrates how the different layer extremes in a backplane will have significantly different performance capabilities. This variation increases as the backplane thickness grows, posing a significant hurdle for chip vendors.
Figure 5: Impact of layer connection on channel throughput.
For TFI-5 and XAUI , the bit rate ranges from 2.488 to 3.125 Gbit/s. At these speeds shaping the signal at the transmitter can typically compensate for the loss of the channel. This technique is known as pre-emphasis, or alternatively de-emphasis, and is an example of pre-equalization.
Figure 5 above demonstrates the low-pass filter nature of a channel. As the frequency of operation increases, so does the amount of channel loss. At the 6+ and 11+ Gbit/s speeds, transmit pre-emphasis by itself does not sufficiently compensate for the loss of the channel.
To compensate for the additional loss, equalization will be employed at the receiver. There are various flavors of receive or post-equalization techniques, such as linear filter equalizers, decision feedback equalizers (DFE), and feed forward equalizers (FFE). Thus, an optimum combination of pre and post-equalizations will work the best to counter the interconnect losses associated with these higher speeds of operation.
The CEI 11G+ LR specifications will primarily be deployed for Greenfield backplanes, which refer to the new backplane designs that leverage off of new developments in silicon circuit techniques, PWB board materials, connector designs, design knowledge, and understanding of channels, to enable these speeds. Electrical signaling at a serial line rate of 11+ Gbit/s will require the appropriate synergistic performance between the passive components of the channel and the techniques employed in the semiconductor devices that interact with the channel.
A major objective of the CEI LR specifications is to make appropriate decisions regarding how each part of the system can contribute to advancing to the next speeds. For example, silicon, connectors, materials and construction techniques are all part of the solution. Improvements in each will have to be evaluated in the context of system cost, system power dissipation and system manufacturability; 11G+ LR, however, is less constrained on cost and more constrained on power.
The CEI project defines the electrical characteristics for 4.976 to 6+ Gbit/s and 9.95 to 11+ Gbit/s signaling for chip-to-chip and board-to-board applications. By defining these characteristics, the OIF is enabling the development of the next generation SFI, SPI, and TFI interfaces. With the CEI project underway, the OIF has begun the CEI-P Project, which will define the protocol for these next generation interfaces. These two projects will enable higher capacity systems by reducing the overall size, cost and power of all of the internal electrical interfaces that are used to build them.
About the Authors
Steve Joiner is the OIF Technical Committee Chair and chief marketing strategist at Bookham Technologies. Steve earned his BA, MA and Ph.D. degrees in physics from Rice University in Houston and can be reached at firstname.lastname@example.org
John D'Ambrosia is the OIF Marketing, Awareness and Education (MA&E) Committee Chair and the Manager of Semiconductor Relations for Tyco Electronics. John received a B.S. in Electrical Engineering Technology from the Pennsylvania State University in and a Master's Degree in Engineering Management from the National Technology University. He can be reached at email@example.com
Tom Palkert is an OIF Board Member and Systems Architect Manager for the Mixed Signal Division of AMCC. Tom received his BSEE and MSEE degrees from the University of Minnesota and can be reached at firstname.lastname@example.org.
Bodhi Das is an OIF member and a Staff IC Design Engineer and Program Manager at Xilinx. Bodhi has a Bachelors degree in electrical engineering from Indian Institute of Technology, Kharagpur, India, and a Masters degree in electrical engineering from Iowa State University. He can be reached at email@example.com.