The 2-Gbit NAND device is organized as 2048 blocks, with 64 pages per block (Fig. 3).
Each page has 2112 bytes total, comprised of a 2048-byte data area and a
64-byte spare area. The spare area is typically used for ECC,
wear-leveling information, and other software overhead functions,
although it's physically no different from the rest of the page. NAND
devices are offered with either an 8- or 16-bit interface. Host data is
connected to the NAND memory through a bidirectional data bus, 8 or 16
bits wide. In 16-bit mode, commands and addresses use only the lower 8
bits. The upper 8 bits are only used during data-transfer cycles.
Fig 3. The 2-Gbyte NAND device is organized as 2048 blocks.
Erasing a block requires about 2 ms. Once the data is loaded in the
register, programming a page requires about 300 —s. A page read requires
approximately 25 —s, in which the page is accessed from the array and
loaded into the 16,896-bit register. The register is then available for
the user to clock out the data.
In addition to the I/O bus, the NAND interface is comprised of six major control signals:
- Chip enable (CE#): If CE is not asserted, the NAND device will remain in standby mode and not respond to any control signals.
- Write enable (WE#): WE# is responsible for clocking data, address, or commands into the NAND.
- Read enable (RE#): RE# will enable the output data buffers.
- Command latch enable (CLE): When CLE is high, commands are
latched into the NAND command register on the rising edge of the WE#
- Address latch enable (ALE): When ALE is high, addresses are
latched into the NAND address register on the rising edge of the WE#
- Ready/busy (R/B#): If the NAND device is busy, the R/B# signal
will be asserted low. This signal is open drain and needs a pull-up
Data is shifted into or out of the NAND register 16 or 8 bits at a time.
When doing a Program operation, the data to be programmed is clocked
into the data register on the rising edge of the WE#. Special commands
are used to randomly access or move data around within the register to
make random access easier.
Data is output from the data register in a similar fashion using the RE#
signal, which is responsible for outputting the current data and
incrementing to the next location. The WE# and RE# clocks can run as
fast as 30 ns. When RE# or CE# aren't asserted low, the output buffers
will be tri-stated. This combination of CE# and RE# enables the output
buffers, allowing NAND flash to share the data bus with other types of
memory like NOR, SRAM, or DRAM. This feature is sometimes called "chip
enable don't care." The primary purpose of this reference is to
accommodate older NAND devices, which require CE# to be asserted for the
All NAND operations start supplying a command cycle (Table 1).
This is accomplished by placing the command on I/O bits 7:0, driving CE#
low and CLE high while issuing a WE# clock. Note that commands,
address, or data are clocked into the NAND device on the WE# signal's
rising edge. Table 1 also shows that Most commands require a number of
address cycles followed by a second command cycle. Note that with the
exception of the Reset or Read Status commands, new commands shouldn't
be issued if the device is busy.
Looking at the addressing scheme for 2Gb NAND devices, the first and
second address cycles specify the column address, which specifies the
starting byte within the page (Table 2). Note that because the
last column location is 2112, the address of this last location would be
08h (in the second byte) and 3Fh (in the first byte). PA5:0 specify the
page address within the block and BA16:6 specify the block address.
While the full 5-byte address is required for most Program and Read
operations, only the first and second bytes are needed for operations
that randomly access data within the page. The Block Erase operation
only requires the three most significant bytes (third, fourth, and
fifth) to select the block.