Mixed Signal Hard Macro: A circuit design and artwork that is incorporated into an integrated circuit to perform a specific function not realizable solely with digital logic. Examples include oscillators, PLL’s, voltage references, Ethernet transceivers, USB transceivers, Analog-to-Digital Converters.
The other day Bob, a business associate, was describing an experience he had with a newly hired IC designer. The designer had integrated a high-speed I/O block into a 130nm test chip and released it for fabrication. The compressed time schedule precluded a formal design review. Bob asked, “What did you do for ESD protection.” The designer replied, “It’s a test chip – it doesn’t need any ESD protection.” Of course, even a test chip needs ESD protection because fields generated in packaging and shipping can damage IC devices. Bob held his breath until the prototypes arrived. Thankfully, they were usable.
In this case, the designer overlooked ESD protection because he was inexperienced. But I’ve encountered a group of design weaknesses that even experienced IC designers and managers overlook. Because I’ve seen the same mistakes made by different engineers working for different companies, I believe it would be worthwhile to compile a list of them. Many of the problems are related to the way that the designs interact with their environment.
The trend toward IP outsourcing has made it more important to be aware of these issues. IP outsourcing creates both geographic and corporate barriers to communication, so the designer sees less of the full development cycle. The designer also becomes more focused on a particular specialty, making it less likely that subtle system-level issues will be checked.
If anyone who works with me sees a mistake in here that they recognize in their design, please don’t take it personally. I’ve included only those mistakes that I’ve encountered multiple times from different designers, all of whom are very experienced. So if you’ve made one of these yourself, you are in good company.
Overlooked item #1: failure to consider the effects of powering down the hard macro while voltage is applied to the input pins — The Product that Won’t Turn Off
SYMPTOMS: The user turns the device off, but leaves it connected to another piece of equipment. The device begins drawing power through its input pins. Symptoms may include LED’s being remaining partially illuminated. In more serious cases, the device fails to turn on properly. The problem goes away when the cable is disconnected from the device prior to powering it off.
WHAT HAPPENED: It is important to consider what happens when a hard macro is powered down when the input pins are connected to another device. If care is not taken, the hard macro may conduct power from the input pins to the power rails. This can damage the device if the conducted current exceeds the allowable current through that input pin. The most interesting type of behavior I’ve seen involved a device that appeared to remain turned on even when the power switch was off. The ‘Power’ indicator was being driven by current conducted through input pins on the device. Disconcerted users found that even pulling the power plug wouldn’t make the dimly lit LED go off. The problem was intermittent and depended on the particular data pattern present on the interface when the device was powered off. The more 1’s on the interface, the brighter the LED’s. Less interesting outcomes include systems that fail to turn on correctly, because the quasi-powered-on state confuses circuits power-on reset systems.
Figure 1 – Example of a hard macro powering up the rest of the system. The diode was placed between the SIGNAL and the IC’s power plane as an ESD protection mechanism. When the IC is powered off, the IC back powers the circuit board with current drawn from the SIGNAL line
Click to Enlarge
WHY AND WHERE IT MATTERS: Hard macros are integrated into chips, which are soldered onto printed circuit boards and loaded into products. Customers buy the products and connect them together. Examples include stereo equipment, computer equipment, security systems, networking equipment, etc. If the hard macro conducts current through its input pins, then so will the product. Since each product has its own power supply, it is likely the customer will power down one piece of equipment, while leaving other pieces powered up.
HOW TO FIX IT: A Spice simulation can identify this problem. When running the simulation, it’s important to use a Spice netlist that has been extracted from artwork, and includes parasitic P-N junctions, since these can create a path for back-powering the device.
Figure 2 – Simulation showing supply voltage connected to 0V and inputs being driven by external source
Click to Enlarge
Overlooked item #2: There is no such thing as a minor change
SYMPTOMS: Following a routine release of a mature design, portions of the design begin to exhibit problems even though there were no planned changes to those areas.
WHAT HAPPENED: Early versions of IP are subjected to intense scrutiny with careful design reviews and test chips. When a piece of IP enters the maintenance phase of its life cycle, companies refocus their design resources on newer projects while making small changes to the existing IP to fix minor bugs and meet customer needs. This creates an environment where an IP designer can make what seems like an inconsequential change which that introduces a defect into the system.
WHY AND WHERE IT MATTERS: With the rising cost of mask sets and increasing time to fabricate test chips it’s more important than ever to avoid risky design practices.
HOW TO FIX IT: IP design groups should use careful revision control as part of their release process. Revision control is more than revision monitoring. A mature design accumulates a verification portfolio from simulation test-benches, test chips, and product implementations. Any time a revision is made to a verified design, part of the verification portfolio is invalidated. The benefits from the revision must be weighed against the potential risks. If the decision is made to execute the revision, a plan should be put in place to minimize the risks by re-validating the verification portfolio. .
Table 1 illustrates how the effect of revisions on the verification status of a piece of IP can be tracked. Many defects can be found by inspection by collaborating among experienced designers.
Table 1 – Oscillator Revision Control Chart
Click to Enlarge
This is a verification history demonstrating how each change needs to be evaluated against all the different possible verifications that have been performed on the chip.
If someone were to attempt to use Revision 411, and they examined the revision history, they might be lead to believe that the only relevant change was an inconsequential update to the datasheet. By tracking the impact of changes in the Columns 4, 5 and 6, it can be seen that many aspects of the design could introduce risk.
Revision 405 is released to a test chip, and all three functional areas pass. All of the results from that test chip remain valid until Revision 408, which invalidates the “Register Access Testing Results” but not voltage margins or ESD results. If Revision 408 is to be used, the Register path should be carefully examined. Revision 409 invalidates the ESD results by changing the series resistor in the input path. If Revision 409 is to be used, ESD results should be examined carefully to determine how close the original design was to the margins. Finally, by Revision 410 all the results are invalidated.
The highlighted changes in this figure represent risk items, because they have not been verified. Special attention should be paid to these items to minimize the risk to the project.
A revision control system should not rely on self-reporting. It should include automated scripts to compare versions of the design to catch any minor changes that designers might make. In some cases, these changes might be accidental and wouldn’t be reported. Anything that can be compared should be compared – RTL source, Schematics, Layout, test benches, etc.
Overlooked item #3: Oversimplification of the system environment in the spice simulations
SYMPTOMS: The pre-silicon simulations look great, but the test chip comes back and exhibits erratic behavior. Examination of the Spice test benches shows that the models used for the system (power supply, input/output loads) fail to account for one or more types of important system behavior.
WHAT HAPPENED: A wide range of unstable behaviors can be missed if parasitic elements are omitted from the Spice verification test benches. Stray off-chip capacitances from the package and components can drive feedback loops to oscillate. At a minimum, PCB traces and cables should be modeled with delay, potential impedance mismatch, and parasitic inductances and capacitances at either end. A frequent mistake is to model a transmission line with a single resistor. The model is sometimes used because a perfectly terminated (or infinite) transmission line looks like a resistor at high frequencies. But the resistor model is mildly inaccurate when it omits parasitic elements inductances, capacitances and mismatches which cause reflections. The model is wholly inaccurate for finite length transmission lines that terminate in an open circuit.
Engineers sometimes indicate that they can not include system effects because they don’t have perfect measured data on how much noise, capacitance, mismatch, etc. is in the real system. But perfect measurements are not essential since parasitic values by their nature aren’t controlled. Adding any reasonable estimate for the parasitic element is preferable to omitting the parasitic entirely. Even if the estimate is inaccurate, the change in behavior can draw enough attention to a circuit to ensure that its weaknesses are corrected before tapeout. Table 2 provides suggested ballpark values for common parasitic elements.
Table 2 – Estimates and Sources for common parasitic elements
Click to Enlarge
Power Supply Turn-on: Integrated circuits in deep sub-micron processes can use two or even three power supplies 1.2V, 2.5V and 3.3V are all common. Failure to adequately model power supply sequencing in Spice simulations can leave serious problems undetected. Macro designers may assume that the 3.3V supply will always be at a voltage greater than the 2.5V supply, which may not be true depending on the configuration of the circuit board’s power supply network. Ideally the macro should be designed to be immune to the power supply sequencing order. If this is not possible, supply sequencing requirements should be documented in the design’s datasheet.
Figure 3 – Example of a circuit where turning on the power supplies in a different order could cause excessive power consumption. The designer added the diode between 1.2V and 3.3V as an ESD protection mechanism. In quiescent state, the 1.2V rail is always below the 3.3V rail, so the diode is reversed biased. But if the 1.2V supply is powered up first, the diode will be forward biased.
Click to Enlarge