The Class D amplifier topology theoretically offers ideal characteristics for audio: 100% efficiency, 0% THD, and no audible noise. While practical Class D implementations can come attractively close to realizing the ideal, they also occupy less space than competing topologies—most notably Class AB—owing largely to their superior efficiency. The power device’s characteristics, however, can limit the performance of a design. Careful attention to device selection is essential to optimizing amplifier performance.
As an amplifier’s output power capability increases, Class D’s efficiency advantages over Class AB becomes increasingly profound. Despite the historical image that switching amplifiers can never outperform linear amplifiers, well-designed, modern Class D amplifiers deliver excellent audio performance with advanced silicon technologies.
For better audio performance, the shape and timing of switching waveforms hold the key. In order to obtain good THD+N, the waveform has to be sharp and clean with accurate switching timing relative to the PWM modulator’s output.
Deadtime in the power stage’s output waveform creates a non-linearity due to alternating commutation current from the output inductor. The deadtime subtracts from the modulator’s output pulse width when the speaker’s load current is larger than the inductor ripple current. Consequently, the Class D stage gain varies as a function of the output current—a behavior that creates harmonic distortion. Unfortunately, though reducing deadtime reduces THD, it also increases the danger of shoot-through current.
Start with deadtime
A gate-driver IC with built-in deadtime generation enables known deadtime settings over differing conditions. For example, an IRS20124S Class D audio gate driver from International Rectifier controls the deadtime to compensate for variations and drifts within the driver IC due to changes in conditions such as temperature. This ensures optimum deadtime performance, Figure 1.
Figure 1: The IRS20124S Class D audio gate driver from International Rectifier controls the deadtime to compensate for variations and drifts due to changes in conditions such as temperature.
For higher efficiency, power MOSFET silicon design holds another key to success. A Class D amplifier’s losses include switching and conduction terms. Attempts to minimize the two loss terms make competing demands on the MOSFET design. For example, a larger die results in lower conduction losses due to the lower RDS(ON). However, the increased die size also results in slower transition times and greater switching losses as a result. For each device application, an optimal die size exists that minimizes the total loss.
The importance of carefully selecting the power MOSFET increases with the power. For example, the IRF6645 is suitable for Class D amplifiers in the 100W range, Figure 2a and Figure 2b.
Figures 2a and b: The two-channel, 120W/ch Class D reference design, scheduled for release during the first half of 2006, fits on a 1.5" x 3.125" PCB, requires no heat sink, and locates all Class D stage components on the board’s top surface; the figure below it (Figure 2b) is a detail of the right side of Figure 2a.
The DirectFET MOSFET package exhibits excellent switching edges for faster, cleaner waveforms due to its inherently low parasitic inductance. This package allows four times higher dV/dt with 9dB less EMI emission when compared to TO-220 package.
The resultant amplifier is remarkably space efficient: A two-channel, 120W/channel Class D reference design fits on a 1.5" x 3.125" PCB, requires no heat sink, and locates all components for the Class D switching stage on the board’s top surface. The design uses a self-oscillating PWM modulator to minimize the component count and a 2nd-order integrator for the error amplifier. The advantage of this modulator over a carrier-based design is that the self-oscillating modulator shifts in-band errors out of band while it provides sufficient correction to deliver good performance from a half-bridge power stage.
Follow layout guidelines
The PCB layout is critical to a Class D amplifier design’s success because it affects both the design’s audio performance and its robustness. A vital goal of the layout is to minimize and separate the stray inductances. The excessive spike voltage from stray inductance can be a root cause of catastrophic failure in the switching stage. Separate the sensitive analog PWM modulator section from the switching stage to minimize the noise floor. A good rule of thumb for PCB design is to prioritize route placements in order of total loop impedance, working from the lowest impedance loops to the highest. Then think about how to assign and share the inevitable impedances common to multiple loops.
The reference design, scheduled for release during the first half of 2006, gathers critical power paths, which contain highest di/dt, toward the middle of the board to minimize the stray inductances and loop area. In general, the most harmful noise source in a Class D amplifier derives from the switching currents from the positive to the negative bus voltage such as the body diode’s reverse-recovery current and the current that charges the MOSFET’s output capacitance. This current loop becomes more and more critical with fast, low-impedance MOSFETs. It is important to close this loop locally, covering as small an area as possible, and then prevent the voltage spike from spreading to the rest of the system by using appropriate high-frequency decoupling capacitors. In the design’s final stage, consider using an RC snubber to reduce the remaining switching artifacts.
With careful PCB design, and with the help of feedback correction from the switching node, this reference design can realize THD+N as low as 0.009% at 1kHz, 50W into 4Ω, Figure 3.
Figure 3: THD+N vs. power performance is eventually rail limited as demonstrated by the reference design operating on ±25V rails (red), ±30V rails (yellow), and ±35V rails (green).
Proper PCB layout and accurate switching timing contribute to the low noise floor. The optimized MOSFET design provides sufficiently high power-stage efficiency to allow the amplifier to run without a heat sink.
As silicon technology progresses, Class D amplifier performance will continue to improve. Unlike Class AB amplifiers, the efficiency of Class D amplifiers will also continue to improve, enabling both a smaller footprints and higher performance.
About the author
Jun Honda serves as Senior Staff Engineer at the International Rectifier Corp Consumer-IC Design Center in El Segundo, CA, where he is responsible for Class D audio applications. He has more than 15 years experience designing for consumer audio and professional audio equipment, including five years designing Class D audio amplifiers.