When selecting a linear regulator for any application, whether it be mobile power management (characterized typically by lower-lower applications) or consumer applications (such as set-top boxes where higher currents and therefore higher power dissipation is acceptable), the packaging technology chosen is going to be radically different. From uCSP (micro chip-scale packaging), which allows package sizes proportional to the actual die size, to S-Pak power packaging, the options for packaging available today are numerous and varied. In order to focus on a particular area, let's look at mobile products, so the discussion will revolve around the evolution of packaging from small-outline plastic packaging to wafer-level CSP packaging, and what is the right package for the application.
When designing with a linear regulator in a mobile application, the engineer must take care that the appropriate regulator is designed into the appropriate application. For example, if the input voltage of the regulator is 3 V to 4.2 V (typical voltage for a lithium-ion battery), and the output voltage is 1.5 V, with required output currents varying between 100 mA and 300 mA, it is highly likely that an LDO regulator will not be the best choice for the application. This is due to the relatively large differential input-to-output voltage.
Mobile applications require significant power savings since they are powered from batteries and, as a result, need to maintain higher efficiencies to increase the operating time of the portable device. Therefore, a high-efficiency switchmode converter, such as a switching regulator, would be the best choice.
But in many mobile products, there still exist several linear regulators providing voltages from 3.3 V down to 1.8 V from a single lithium-ion battery. If two different applications are analyzed for mobile phones, we can analyze which package would be best from a performance standpoint.
For example, the RF section of a mobile phone usually requires a 2.7 V to 3.0 V output regulator. The input supply of that regulator is the typical lithium-ion battery, meaning that the maximum voltage applied to the regulator will be 4.2 V. The currents that are typically drawn by the RF section can be as low as 20 mA, to as high as 150 mA. Therefore, the worst-case for power dissipation requirements can be broken down as follows:
Vin = 4.2 V; Vout = 2.7 V; Iout = 150 mA;
To calculate power dissipation in a linear regulator, the following formula is used:
Pd = (Vin − Vout) · Iout + Vin · Ignd
In linear regulators where the ground current is less than one percent of the output current, and the input voltage is less than 5 V, the ground-current term becomes insignificant and can be ignored when calculating maximum power dissipation. For the RF example, the power dissipation is:
Pd = (4.2 V − 2.7 V) · 150 mA
Pd = 225 mW
Most packages designed for the RF applications are designed to dissipate 400 to 500 mW of power dissipation.
Table 1 shows a breakdown of the three different package types used for RF power management in mobile phones.
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Table 1: PCB area and thermal resistance by package type.
The most common is the SOT-23-5. This package is a standard surface-mount package, occupying about 3 mm x 3 mm of PCB area; it has a thermal resistance, theta, of about 235 °C/W. This would give about 425 mW of power dissipation at room temperature and 230 mW of power dissipation at an ambient temperature of about 70° C.
One relatively new package available in the market is the MLF 2 mm x 2 mm package, which occupies less than half the space of the SOT-23 and has significantly lower thermal resistance of about 93 °C/W due to its backside thermal slug pad. This means that for an equivalent application, the MLF package occupies significantly less space and requires less heatsinking, even though it occupies the less space. It is a package that dissipates its own heat more efficiently and relies less on the outside world to do so for it.
For the RF application, the SOT-23-5 barely meets the required power dissipation and becomes very hot. If the junction temperature of the SOT-23 die is analyzed under worst-case conditions and compared to the MLF product under worst-case conditions, then you can see a big difference in die temperature. To calculate junction temperature, use the equation:
Pd = (Tj − Ta)/θJa
Tj = (Pd · θJa) + Ta
Where Tj is the junction temperature, Ta is the ambient temperature, and θja is the thermal resistance between the junction and the package.
For the case of the SOT-23 at worst case ambient temperatures of 70 °C, the junction temperature would be:
Tj = (225 mW · 235°C/W) + 70°C
Tj = 122.9°C
For the case of the MLF-2x2 package, the junction temperature is as follows for the equivalent application:
Tj = (225 mW · 93°C/W) + 70°C
Tj = 90.9°C
The MLF product runs 30° C cooler at the die than the SOT product. The benefits of this are not obvious at first, but when you analyze the contributions of temperature in CMOS regulators, one can see that at high temperature the dropout voltage goes up. The P-channel transistors, most commonly used in CMOS regulators, have a positive temperature coefficient of resistance, meaning the channel impedance increases as the temperature increases. This means the dropout voltage increases linearly with temperature. With an equivalent input voltage, the regulator with the cooler die temperature will have more headroom in comparison to the hotter regulator, and all the performance parameters will be better.
The newest technology available to linear regulators for packaging is wafer level technology. Figure 1 shows the evolution of packaging with time, and the onset of miniaturized packaging last year with overall market acceptance of this package occurring in 2004.
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Figure 1: Trend in LDO package size versus time
The CSP package is a package ideal only for extremely space-constrained applications for several reasons. A die that fits into a SOT-23-5 will typically be a CSP package of 1x1.4 mm. This is a tiny final product, but the thermal resistance of this product is actually higher than the SOT-23-5. This means that CSP actually runs hotter under worst-case conditions, and is actually limited in the amount of power dissipation it can handle for portable applications.
It is also a more expensive technology due to the intense requirements for testing that today is easily handled with SO and MLF technologies. But, with an area that occupies less than one-quarter of a SOT and less than half of an MLF 2x2, it represents a compelling technology. Only a small portion of the market is working with CSP technology, due mainly to challenges of working with such small packaging during the reflow process.
Other companies are avoiding the technology due to price. The CSP technology demands a premium over the standard SO package and many companies are not willing to pay the premium. With time, the pricing of chip-scale relative to the rest of standard packaging should fall in line, but today and for the foreseeable future, CSP will be a more expensive alternative to its plastic relatives.
About the author
John McGinty is with Micrel, Inc, San Jose, CA