(Editor's Note: A related column appears online at Planet Analog, click here.)
The promised advantages of digital technology are only as good as the ability of the analog technologies to faithfully translate the digital language of 1s and 0s into natural analog signals. The advance of the digital revolution has been characterized by Moore's law, which states that the number of transistors on a chip doubles every 18 months.
Analog technologies, on the other hand, are characterized by Murphy's Law—if anything can go wrong, it will. Analog technologies progress at a more measured pace dictated not by process enhancements but by innovations in circuits and physical transistor modeling. These technologies improve incrementally on multiple dimensions of performance, power, and integration.
Integration trends and the case for partitioning
Integration trends are a function of volume and system maturity; in many cases system acceptance and unit volume production never grow to justify recurring generational development. In other applications, such as base stations, instrumentation, and military applications, stringent performance requirements lead to discrete implementations. In cases such as cellular and Wi-Fi, where consumer acceptance is universal, competitive forces drive the continual cost reduction.
As technology becomes more expensive to deploy (such as mask, tool, and engineering costs), the return needed to justify these developments increases. At the same time, competitive forces drive companies to invest heavily early in a standard's life cycle. If a market takes off, and a company's chipset is not ready, the financial result can be dire.
In essence, companies are forced to invest to be ready when a market takes off, and this investment is increasingly expensive, while at the same time, customers are requiring more performance from their suppliers. Obtaining an acceptable return on the R&D investments required to build today's complex communication systems is a very tricky proposition. Depending on the complexity of the SOC—development costs can easily range from $10 to $20 million, and higher, for a 90 nm design.
Thus, success of a new initiative depends on identifying a market where your IP is valuable and then lining up partners to meet customer needs. Fewer and fewer companies are able to handle all aspects of a system development. However, focus on performance cost, time to market (TTM), and financial payback is an absolute requirement.
For emerging communications applications like WiMAX, the first generation systems have typically been developed using multiple ICs. The MAC/modem section may use FPGAs and off-the-shelf DSPs; the RF sections often use discrete components such as LNAs, mixers, and synthesizers, with the ADCs and DACs bridging the gap. As volumes grow, the digital logic is often integrated together on a dedicated ASIC and, in some cases, the ADCs/DACs are included on this digital ASIC, for use with more integrated RF solutions.
For other applications with size constraints, such as mobile phones or USB dongles, the analog and digital functionality can be integrated together, either in one system in a package using multichip modules, or on a single chip. There are many different ways to drive to lower size and cost, but the trend is that as volumes increase, size and cost decline. In some cases, cost is king and RF performance can be sacrificed (i.e., some WLAN consumer applications), although customers don't realize it. In other cases, size is paramount, and integration of functionality is the driver.
There is no one recipe for success. Companies have been successful with many different integration and cost reduction strategies. To be clear, development choices must be made that minimize electronic bill of materials (eBOM), size, and TTM. Intelligent design of system partitioning is instrumental in achieving success.
Traditional partitioning: a time to market risk
The integration of mixed-signal circuits on a digital ASIC, Figure 1, opens doors to many implementation challenges and hence introduces a time-to-market, and more importantly, time-to-revenue risk to the product.
Figure 1: Traditional Partitioning
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Even though the mixed core has been verified on a standalone basis, the performance of the core is a function of the environment in which it is integrated. Issues of power supply routing, parasitic capacitances, and process variations that are not important for a digital-only chip, now have a greater significance.
The time from an FPGA-validated, digital-only design to silicon ranges from two to six months based on complexity, design flow, and automation tools. On the other hand, the cycle time to get a mixed-signal design to first silicon could take up to three times as long—assuming that the analog cores are available and verified in the appropriate process of choice, Figure 2.
Figure 2: Design Cycle Time
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The sensitivity of analog circuitry to noise generated by the switching of millions of transistors in the presence of signals in the range of microvolts requires greater attention and multiple design and layout reviews, thereby increasing the time to silicon and working samples.
The problem is not insurmountable. Multiple techniques are available to mitigate the interaction, but these require careful attention to custom layout of the mask, which takes engineering time and resources. It certainly requires an entirely new set of core competencies in what may already be an overloaded engineering team.
The evaluation board design and layout also has a critical impact on the performance of the mixed-signal portion of the device. The analog I/O on the reference board is sensitive to external noise, and the supply routes to the mixed-signal portion of the design require high isolation. Eliminating analog I/O reduces the noise coupling issues to a minimum. In addition, it solves the problem of interfacing analog cores from different vendors (i.e., RF chip and mixed-signal converter cores).
For example, some of the available ADC cores recommend that, to obtain data sheet specified performance, a discrete 5 V op amp driver buffer is required. For modems using a smaller process, such as 130 nm or 90 nm, the signal swing and common-mode level must be reduced and matched when using different vendor RF chips. These additional considerations require valuable engineering resources.
Being second to market often means steeply discounting product pricing in order to capture market share. Choosing a pure digital or an FPGA design flow can shorten the time to bring a product to volume manufacturing by six to 12 months.
Getting to functional silicon is only the first step, as getting to production with a mixed-signal IC offers its own challenges. Mixed-signal circuits are sensitive to process variations such as thresholds, leakage, resistance of material, and other process parameters. Often, as the performance of the mixed-signal degrades, so does the system.
In high volume markets, the ability to manufacture at multiple fabrication sites is essential to ensure timely delivery and optimize costs. Digital design can be relatively fabrication-site agnostic while porting mixed-signal circuits to different fabs is time consuming and can require extensive redesign and optimization skills. The resources for targeting different manufacturing flows are usually very difficult to put together, and often better spent elsewhere.
Another important issue with traditional partitioning is that it requires a matched pair approach. That is, since the ADCs and DACs are separated from the RF, the real-time loops, such as automatic gain control (AGC) and transmit power control, are forced to be shared between two chips and multiple parties. Significant up-front work is required to optimize a reference design from discrete devices.
These challenges of analog and mixed-signal design lessen the focus from the core competency of the system level design team and can delay the introduction of new products to market.
With the availability of mature RF CMOS processes and advances in analog and RF modeling capabilities, it is now possible to move the data converters and other mixed-signal blocks to the RF IC. The next section will show why replacing the traditional analog baseband interface with a digital interface offers a "smarter" system partitioning
for some communications systems, Figure 3.
Figure 3: Smart Partitioning
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The proposed change includes the appropriate partitioning of functionality such that the RF system on a chip (SOC) provides a complete RF to bits solution, which includes all the required control loops such as automatic gain control, transmit power control, and RF calibration loops. The inclusion of control loops on the radio front end results in ease of use and easier mix and match capability with different digital baseband PHY modems.
A standard format, the ADI/Q™ digital I/Q interface, is available for the interface between the RF front end and the digital baseband. This interface format consists of bidirectional control and data lines and it supports interchangeability and ease of application. The reduction of real-time software control results in simpler system design. All the analog and RF specific controls are partitioned to the RF front end.
(Click HERE to read Part 2)
About the authors
Noman Rangwala, Marketing Manager, (firstname.lastname@example.org),
and Tom Gratzek, Product Line Director (email@example.com) at both at Analog Devices, Inc.