(Click HERE to read Part 1)
Low unit cost and lower development cost
Market segments which are characterized by high demand and production
volumes attract more market entrants. To be successful in defending a lead and increasing market share, the solution providers need to pay attention to full factory cost for the chipset. Smart partitioning can offer significant device cost reduction.
For communication systems, such as WiMAX and broadband wireless access, consumer price points less than $100 are essential. CPE equipment for ADSL and 802.11g Wi-Fi ($20 to $30) are examples of where volumes increased dramatically as prices declined. An emerging market such as WiMAX will also experience similar price pressures. It is expected that the end user CPE prices will be under $100 by mid-2007. To achieve these targets, the chipset pricing will be required to fall into the range of $20 to $25. This is probably much lower than the current costs, and will require quantum improvements so that market prices yield an acceptable profit.
RF-to-bits radio ICs can help enable this transition
For a given process, mixed-signal ASIC design is more expensive than a digital-only ASIC design, with the increased cost adders having four main components:
1. For a particular process, mixed-signal devices are inherently more expensive. The mixed-signal features require additional processing steps such as thicker oxides, low threshold devices, and additional implants. In general, mixed-signal wafer costs can be 20% higher than the digital-only wafer.
2. The fabrication plants invest heavily in the reduction of defect density, resulting in high yields, close to 97% to 98%, depending on die size. On the other hand, analog circuit IC yield is a function of the design itself. To achieve specified performance while making power dissipation trade-offs, analog circuits are designed to perform to specifications over a narrow window of process variations when compared to digital design, resulting in parametric-limited yield, thus increasing the costs for mixed-signal designs. This adds over a 10% increase in costs for mixed-signal designs.
3. The elimination of analog functions from the digital modem results in simplification of production test development and is instrumental in reducing production test time. Enabling test on a generic digital tester rather than an expensive mixed-signal tester can reduce tester cost by 15% to 20%.
Test coverage tools allow a digital designer to create fault coverage scan chains, simplifying production test. Since mixed-signal testing requires measuring various analog specifications in the range of a few microvolts, a mixed-signal test design could take at least five times longer than a digital-only test. The time can be reduced using parallel processing on the testers. Assuming an aggressive test program methodology, the test cost for mixed-signal devices can be in the range of two to three times greater.
4. The integrated converter core is usually intellectual property that is developed by a third party and/or an internal group with associated royalties, and/or NRE. The design and support tools used in a mixed-signal design flow are an added investment when compared with a design toolkit for a digital-only ASIC solution. A suite of tools
required to design a new mixed-signal ASIC, when compared to a digital-only ASIC, can easily exceed $500k.
Additionally, analog circuits do not scale with process shrinks in the same way digital circuits do. Figure 4 illustrates the rising costs of mixed-signal ICs as a function of feature size.
Figure 4: Cost Benefit of Smart Partitioning
(Click to Enlarge Image)
The cost curves are normalized to the cost of a digital-only ASIC in 180 nm. Historically, the digital ASIC cost tends to reduce by a third when migrating from one feature size to the next. In contrast, the mixed-signal IC cost increases as a function of the percentage of mixed-signal die area. This comes from the fact that the noise-limited analog circuitry does not scale with lithography, while the digital circuitry tends to scale quadratically with process.
New processing equipment investments and the increased complexity of the manufacturing process result in a net increase in the die cost per sq. mm from one generation to the next. The digital circuitry scales proportionally to result in a lower cost per transistor. Since analog circuits do not scale with process, the total mixed-signal product cost tends to remain flat initially and increases with subsequent process shrinks.
In high volume markets, companies must remain cost competitive while meeting market pricing and providing a fair return to investors. If a company's cost structure is double the best-in-class competitors, new tactics or new strategies will soon become necessary. Although all the challenges associated with mixed-signal design continue to exist, the benefits of smart partitioning include dramatically lowering the systems cost by taking full advantage of Moore's law — not always available to analog/RF circuits.
In addition to the increased cost per device, the opportunity cost of not selecting an optimum process and longer time to market can doom the financial return on a project. The availability of ready-to-use analog and mixed-signal cores lag behind the digital process by approximately two years, or about one generation. With the availability
of production-ready cores being close to four years out, the smart-partitioning approach enables the system vendors to choose an optimum process based on their needs and not be constrained by availability of a validated analog core.
The opportunity cost associated with the selection of a nonoptimum process is high. For example, in the broadband wireless space, manufacturers have announced a 90 nm core design. The difference in product cost between a 90 nm digital SOC design and 130 nm can be greater than 200 percent! At 65 nm, the multiplier can be even higher.
The proposed change offers an opportunity to use the additional time and resources to focus on developing the next generation product—potentially putting it one product generation ahead of competitors who are spending valuable resources fighting issues inherent in a mixed-signal ASIC design.
Performance advantages of the shift to a digital radio baseband interface
Along with the cost advantage in development, support, and per unit cost, smart partitioning enables a high performing system solution.
For advanced OFDM systems with high peak-to-average ratio, the high linearity achieved on the RF device, as well as the advanced synchronization and channel estimation algorithms on the digital baseband (DBB), must not be compromised by the dynamic range of the ADCs and DACs. Careful management of the headroom must be considered to enable robust performance in the presence of noise, fading channels, and interferers.
With the integration of an autonomous AGC loop, the dynamic range of the ADCs can be matched with the capability of the RF front end, thus enabling high data rates such as 64 QAM. There are many vendors that have struggled with bringing up their reference designs because of the complex interactions between the DBB and the RF IC. In addition, advanced techniques, such as symbol-to-symbol AGC, can be utilized to improve the performance of the system in fading channels which are common in mobile environments.
Unlike a distributed AGC (i.e., AGC algorithm implemented on two separate devices), the proposed partitioning enables a fast convergence of the AGC, thus allowing the DBB to spend more time on channel estimation and synchronization, thus improving the system performance by many decibels, which translates into greater range and rate.
Filtering is required to eliminate undesired signals from adjacent or alternate channels. To address this issue, careful trade-offs must be made between linearity and filtering complexity. For low cost zero-IF (ZIF) architectures, the final channel selectivity is performed by using digital filters. Filtering like gain must be distributed between the RF and subsequent digital filters. Smart partitioning enables the optimization of the filtering requirements between the analog and digital filtering, utilizing the converter dynamic range to the maximum.
Power dissipation is also an important parameter for mobile systems. Power dissipated on a digital chip is directly proportional to the square of the supply voltage and directly proportional to the gate capacitance. Thus, for a process migration from 130 nm to 90 nm, the result could be a power savings of a factor of eight. With a smart partitioning philosophy, the DBB, when implemented in 130 nm and dissipating in the range of 1 W to 1.5 W, can be reduced aggressively down to 200 mW, when moved to a 90 nm process.
The digital revolution has resulted in solutions with millions of gates put together on fine line processes. These SOC solutions are expensive to develop and put tremendous pressure on return on investment. To succeed, one must choose the appropriate market segment, apply focus on a core competency to deliver a differentiated product at low cost in a timely manner. Partnering to minimize risk and executing to a schedule is an attractive option.
Partitioning with an "RF to bits" radio offers the four key ingredients for success—high performance solution, focus on core competency, lowest power cost, and fastest time to market.
The appropriate partitioning of analog and digital functionality solves many of the issues related to integration of analog circuits on digital ASICs and results in faster time to market and longer time-in-market. It enables the optimization of the system to achieve high performance.
For digital baseband vendors, with expertise in digital modems and media access controllers, smart partitioning offers the advantage of focusing critical resources on tasks and projects that further enhance their value proposition.
In high volume applications, the choice of process is critical. The ability to migrate to newer processes quickly results in new cost and performance points which will provide competitive advantage. The smart partitioning philosophy is being adopted by multiple standards bodies such as the Digi-RF group in mobile handsets, the JC-61 group targeting WLAN and WiMAX, as well as in various proprietary systems. Analog Devices offers the ADI/Q interface which allows easy implementation of this cost- and performance-optimized strategy.
About the authors
Noman Rangwala, Marketing Manager, (email@example.com),
and Tom Gratzek, Product Line Director (firstname.lastname@example.org) at both at Analog Devices, Inc.