(Note: you can read Part 1 of this two-part article by clicking here)
The gate-control block, or the level-shift block, controls the VG of the MOSFET to switch it ON or OFF. The output of the gate control is directly determined by the input it receives from the input-logic block.
During the ON period, the main task for the gate control is to level-shift the EN to produce a high (N-channel) or low (P-channel) VG in order to turn the switch fully ON. Similarly, during the OFF period, the gate control produces a low (N-channel) or high (P-channel) VG to turn the switch completely OFF.
Many high-side load switches incorporate a "slew-rate control" or "soft-start" function within the gate-control block. The slew-rate control function limits the ramp-up speed of the VG when the switch is turned ON. As a result, the ID builds up gradually. Its purpose is to protect the load from an excessive "inrush current," which may cause faulty conditions such as latch-up.
The load is sometimes not only resistive, but highly capacitive as well. So, when the switch is turned OFF, the charges accumulated in the capacitive load do not get discharged quickly, which may cause the load to shut off incompletely. To overcome this, some of the high-side load switches include an "active load discharge" function, the purpose of which is to provide a current path to discharge the capacitive load quickly, when the switch is turned OFF. This is typically accomplished by a small low-side FET. Figure 4 illustrates this approach, where a bottom N-channel FET, with its gate tied to the gate control core and its drain tied to the load, is turned on to discharge the capacitive load when the main switch, the top P-channel, is turned OFF.
Figure 4: Block diagrams of the MIC94060/1/2/3 P-channel, high-side, load switches.
(Click to Enlarge Image)
The only function of the input-logic block is to interpret the EN and pass the correct logic level to the gate-control block, so that the gate control can switch the pass element ON and OFF with respect to the input-logic level. The implementation of the input-logic block can be as simple as a pull-down resistor.
In certain cases, a buffer is needed in between the EN and the gate-control block. The reason is that the EN may not provide enough driving current for the gate control to drive the VG, in which case the buffer serves as a source of additional driving current.
For an engineer that uses the high-side load switches in designs, there are always parameters that matter to more than others.
The first critical parameter is the ID. This is a system-level parameter that is chosen at the very beginning of the design cycle. The ID of the high-side load switch is determined by factors such as the physics of the MOSFET (N-channel or P-channel), the size of the MOSFET, the physical properties of the bonding wires (length and thickness), and the thermal capability of the package. Typically, high ID switches are N-channel and come in thermally enhanced packages, while low ID switches are P-channel type and offered in small-footprint packages.
The next critical parameter is the RDSON. When the ID is chosen, the lower the RDSON the better. This is because a lower RDSON will increase overall efficiency, reduce the voltage drop-off between the VIN and the load, and relieve the thermal stress to the switch.
With the ID and RDSON decided, a designer typically looks at four key parameters of the switch: the dynamic responses, the shutdown supply current, the shutdown leakage current, and package size.
For the high-side load switch, dynamic responses refer to the time elapsed for the load voltage to rise from the GND to the full VOUT (= VIN " RDSON * ID) or fall to the GND from the full VOUT, with respect to logic level changing on the EN.
When the EN is asserted, after a propagation delay, or turn-on delay time (tON_DLY), which is introduced by the gate-control and input-logic blocks, the VG is then shifted to a level that is high (or low) enough to turn ON the switch. At this time, the output voltage on the load (VS for N-channel and VD for P-channel) starts rising, and the time it takes for it to reach to the full VOUT is termed the turn-on rise time (tON_RISE). Depending upon the system requirements, tON_DLY and tON_RISE need to be short for applications that demand fast responses, or relatively long for applications that need soft-start to limit in-rush current.
Similarly, when the EN is de-asserted, after a propagation delay, or turn-off delay time (tOFF_DLY), the VG is shifted to a level that is low (or high) enough to turn OFF the switch. Now, the output voltage on the load starts falling from the full VOUT, and the time it takes for it to come down to the GND is called the turn-off fall time (tOFF_FALL). Usually, the tOFF_DLY and tOFF_FALL need to be short so that the load can be turned off quickly. If the load has a major capacitive element, then the active-load discharge function can help reduce the tOFF_FALL.
The shutdown supply current and the shutdown leakage currents are also important factors to consider, particularly when designing battery-powered equipment which requires long battery-running time. The shutdown supply current is consumed by the internal circuitry when the switch is OFF. The shutdown leakage current is what the MOSFET passes to the output when the switch is OFF. The lower the shutdown supply and leakage currents, the higher the overall system efficiency. For battery-powered applications, this results in longer battery-running time.
As for the package size (footprint and profile), in most applications it is clear: the smaller the package, the better. This holds especially true for P-channel switches that are used in low-current systems, such as battery-powered handheld devices, in which space is premium.
The Reference below provides more information on the MIC94060/1/2/3 family and Micrel's high-side, load-switch products
Micrel, Inc., High-Side Power Switches,
About the author
Qi Deng is a senior product-marketing manager for mixed-signal products at
Micrel, Inc, San Jose, CA.