Most people are familiar with applications connecting a crystal to a crystal oscillator (XO) IC to generate a frequency. However, many applications also use XO ICs with a reference input, rather than a crystal, connected to the oscillator input pin, as shown in Figure 1.
Figure 1: Schematic showing an IC driving the reference input of a crystal oscillator IC. The Xout pin, used for crystal inputs, is left floating.
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For this reason, this pin is often labeled Xin/REF to indicate that it may be used with either a crystal (i.e. Xin) or reference (i.e. REF) inputs.
There are many reasons to use reference inputs with XO ICs. The wide variety of XO ICs available provides designers many options in filling out a clock tree. In such cases the XO is treated just like any other clock IC. For example, many XO ICs integrate additional functionality (including fan-out buffers such as PhaseLink's PL611s, multiple PLLs such as PhaseLink's PL613, and spread-spectrum PLLs such as PhaseLink's PL671), making them attractive for saving board space, reducing component count, and saving cost.
Additionally, connecting a reference input to an XO IC is the only option when the input waveform does not meet industry-standard logic levels (such as LVCMOS, LVDS or LVPECL). For example, TXCO outputs are ∼1 Vpp clipped sine waves, making them incompatible with ICs designed for standard logic-level inputs. Therefore, TCXO outputs are typically ac-coupled into an XO IC, since an XO's input is an amplifier stage accepting signals down to a few 100 mV.
In all of these applications, the potential for introducing high output jitter exists if the following two conditions are met.
a) The XO device and the device driving it share the same power supply and bypass capacitor network, and
b) The reference input and XO output frequencies are different.
This increase in output jitter is related to the fact that an XO input pin has a fairly large input capacitance, in the range of 10-40 pF, as required by its internal oscillation circuitry. Although this internal oscillation circuitry is not needed for reference inputs (it is only required for crystal inputs), its associated large input capacitance is nevertheless still present.
The output buffer in the IC driving the XO must source a lot of current to drive this load on the input pin, which leads to voltage droop and ground bounce in the power supply rails. This noise can be seen as power supply ripple at the driving IC's output frequency. When VDD and bypassing network are shared between driving and XO devices, a path is created for this noise to couple from the driving chip to the XO device.
Furthermore, if the output frequencies from these devices are different, this noise modulates the XO output and appears as a distinct mode in the resulting jitter's multi-modal distribution. Equivalently, the simultaneous switching noise created by the driving IC couples to the XO via the power distribution network, introducing a deterministic component of jitter into the XO output waveform.
One solution that can minimize this effect is to use separate VDD rails and bypassing networks for the driving IC and XO devices. The bypass capacitor value for each network can then be optimized for the specific device being decoupled, instead of having to make a compromise that doesn't quite fit either device. For example, if an XO is used to multiply its input frequency, the XO bypass capacitor can be chosen to be smaller than the one used for the IC driving the XO, since the XO output buffers are switching at a higher frequency.
This approach can be used when the driving IC and XO are packaged separately, as found on system boards for example. When both devices are integrated into the same module, as common in many oscillator products, only one VDD pin is available. In this case both devices share the same power supply rails (the bypassing network is often shared as well to minimize the module size). An alternative approach must therefore be used.
Figure 2 illustrates an alternative approach that works to minimize the origin of this noise source, which also applies to cases where both devices are packaged individually.
Figure 2: Modified schematic with series resistor (Rs) added to prevent jitter degradation.
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A resistor (Rs) placed between the driving IC and XO, in combination with the internal XO input pin capacitance (Cxin), forms a low-pass filter with cutoff frequency of 1/(2 · π RsCxin). This filter slows down the input clock edges at the Xin/REF pin, which significantly reduces voltage-droop and ground bounce on the power supply rail. The deterministic component of jitter introduced by the driving IC's switching frequency is thus minimized or completely eliminated.
The primary goal in selecting this resistor value is to produce a low-jitter full-swing input for the XO IC. Select a resistor value to set the cutoff frequency somewhere above the fundamental frequency output of the driving IC. As the resistor value increases, the edges slow down, reducing the output buffer's modulation on the power supply rails. However, slowing edges down also has the effect of making the input buffer threshold level more susceptible to noise, which introduces another source of jitter. Therefore, a balance must be achieved for optimal performance.
Begin by selecting a small resistor value and measuring the output XO jitter. Increase this resistor value until its influence on the output jitter has little effect. The optimum value depends on many design factors, including noise environment, buffer drive strength, decoupling, and layout, so you may need to experiment with different resistor values for each new design. In general, use the smallest value of resistor that has an effect in reducing the output jitter.
To quantify the improvement one might expect using this technique, we measured the output jitter from a 9x14 mm2 oscillator module, consisting of a 5x7 mm2 VCXO at 38.88 MHz followed by an PLL-based XO multiplier configured to output 155.52 MHz. PhaseLink's PL680-38, a high-frequency low-jitter PLL multiplier XO, was used in this experiment.
Measurements were taken with and without a 100 Ω resistor (Rs) between the VCXO and XO, corresponding to Figures 1 and 2 respectively. Table 1 summarizes the results for three common types of jitter measurements. The results show this simple technique reduced jitter at least 40%.
Table 1: Measured Jitter Data (ps peak-peak)
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Figure 3 shows the various jitter distributions resulting from each measurement.
Figure 3: Jitter distributions without (left column) and with (right column) a series resistor between VCXO and XO devices in a 9x14 mm2 oscillator module. Note that the x- and y-axis scales are different for each plot.
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Notice the module including this resistor shows fewer modes in its distribution, compared to the same module without this resistor. The deterministic component of jitter resulting from the VCXO-induced switching noise has been significantly reduced.
Note that this analysis applies equally to VCXO ICs, as well as any other IC device employing crystal oscillator circuitry at its inputs.
About the author
Dr. Gary Giust, an authority on jitter minimization, is a product marketing manager at PhaseLink Corp., Fremont, CA, and is responsible for high-performance timing solutions and an expert on jitter minimization. He can be reached at firstname.lastname@example.org.