# A mathematical approach to designing capacitor arrays for switching converters

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Consumer electrical devices such as portable music players and notebook /desktop computers have ASICs, processors, memories, and LED backlights. These components constitute system loads which require valid voltage to guarantee normal operations, usually provided by voltage-altering converters. These converters often employ switching mode topology, with capacitors used to decouple loads, mainly in an event of transients, or time-varying load current.

System designers often see challenges in designing capacitor arrays to be implemented on the output of a buck converter, because mathematical tools for calculating the necessary and sufficient amount of capacitance are not yet established. As a result, system designers might overlook the fact that insufficient capacitance, resulting in invalid voltage, is causing unstable operations of loads, or they are simply wasting component cost and PCB area by implementing surplus capacitance, therefore raising a unit cost of an consumer device unnecessarily.

Voltage stepdown converters (buck converters) are equipped with voltage feedback systems on their own. The voltage feedback systems detect the voltage on the load, compare it against the reference voltage, amplify the error, and correct the voltage on the load by adjusting the duty cycle (**Figure 1**).

*Figure 1*

*(Click to enlarge image)*

(We will not cover how to optimize the feedback loop, that's another topic.) Advanced simulation and calculation tools provided by power IC companies allow easy optimization of feedback systems for given buck converters.

Many system designers don't consciously acknowledge that Bode diagrams, or frequency-domain analyses and transient-voltage waveforms, or time-domain analyses, are all similar. They are analysis in two different domains: a frequency domain and a time domain. The frequency-domain analysis the time-domain analysis are mathematically transferable by the Laplace transfer function.

Bode diagrams or frequency-domain analyses are convenient in visually expressing a zero"crossing frequency and a phase margin of a given system, but give little insight as to how loads behave for a given step-load current. They may be useful for meeting internal design rules.

**Why analyzing a step response is so important? **

Processors require relatively tight voltage tolerances, set by an upper threshold and a lower threshold, or a nominal voltage with a ± 50 mV window, for example. On the other hand, hard-disks or PCI bus voltage rails only require the nominal voltage with several-hundred mV-wide windows to operate reliably. If a feedback system is given a step current, a corresponding response (a step response) appears on the output of the feedback system, or the output voltage in this case. Therefore, if a step current, or an emulated load current, is applied on the output of the converter, a voltage pattern appears on the output of the converter. If the minimum and the maximum of the voltage pattern stay within the tolerance window, that load is will function properly.

A resistor and a switch FET can generate a step-current function. The value of a resistor and the slew rate of the gate of a FET should be calculated to match the amplitude and the edge rate of a real load. In using an electronic load, care must be taken because long cables or parasitic inductance might deform a step current, and therefore a step response cannot be observed on the output. This is especially true when the edge rate of the load is high.

In equilibrium states, the inductor current of a switching converter and the load current match, except for the switching ripple-current element. If the inductor current strays away from the load current, the energy inequality or differential energy causes the capacitor voltage to change, and the energy from the output capacitor fills in the difference in the form of charge/discharge current.

**Figure 2a** and **Figure 2b** illustrate two transient-load cases, one with an optimized feedback loop and a minimum energy inequality, and the other without an optimized feedback loop and an extra energy inequality. The shaded areas indicate energy inequalities between an inductor and a load.

*Figures 2a and 2b*

*(Click to enlarge image)*

(We assume in this article that the feedback loop is optimized as in **Figure 3a**. **Figure 3b** shows in a loading transient event the amount of current to be supplemented by the output capacitor. **Figure 3c** shows, in an unloading transient event, the amount of current to be absorbed by the output capacitor.

*Figures 2a, 3b, and 3c*

*(Click to enlarge image)*

The mathematical expression of the current through the inductor is obtained by integrating the voltage across it, divided by the inductance. In a loading transient event, the duty cycle of the converter becomes 1. Thus, the current supplemented by the output capacitor in Figure 3b, if the beginning of loading transient is timed at t=0 is:

*(Equation 1)*

In the contrary case, in an unloading transient event, the duty cycle of the converter becomes 0. Thus the current absorbed by the output capacitor in Figure 3b, if the beginning of unloading transient is timed at t=0, is:

*(Equation 2)*

Where V_{in }is the input voltage of the buck converter, V_{out} is the output voltage of the buck converter, L is the inductance value of the buck converter, I_{1} is the lower output current level, and I_{2} is the higher output current level.

**Figure 4** shows an equivalent circuit of an output capacitor.

*Figure 4*

*(Click to enlarge image)*

C is the capacitance and R_{esr} is the equivalent series resistor. The voltage drop across R_{esr} due to capacitance across the output capacitor is obtained by integrating Equation 1, when the output capacitor discharges during a loading transient event.

The total voltage drop across the output capacitor is the sum of the voltage drop across the ESR and the above capacitive voltage drop, therefore:

*(Equation 3)*

*(Click to enlarge image)*

Equation 3 is a quadrant function with a peak occurring at a local pole. The local pole of the above quadrant function occurs at:

The max voltage drop at t= tlp_d is:

*(Equation 4)*

*(Click to enlarge image)*

If tlp_d is negative, the max voltage occurs actually at t=0 because of monotonic decay function after t=0, therefore, the max voltage drop is:

*(Equation 5)*

Similarly, the voltage rise due to capacitance across the output capacitor is obtained by integrating Equation 2), when the output capacitor charges during an unloading transient event.

The total voltage rise across the output capacitor is the sum of the voltage rise across the ESR and the capacitive voltage rise, therefore,

*(Equation 6)*

*(Click to enlarge image)*

Equation 6 is a quadrant function with a peak occurring at a local pole. The local pole of the above quadrant function occurs at:

The max voltage rise at t= tlp_r is:

*(Equation 7)*

*(Click to enlarge image)*

If tlp_r is negative, the max voltage rise occurs actually at t=0 because of monotonic decay function after t=0, therefore, the max voltage rise is:

*(Equation 8)*

Let's take a graphical processor unit (GPU) as a practical case. The voltage powering a GPU is converted from 3-cell lithium-ion battery, typically, 12 V, down to 1.5 V. The current consumption in low-power mode is 0.5 A, and the current consumption in high-power mode is 8.5 A. The voltage tolerance window for the GPU is 1.5 V ± 75 mV to guarantee normal operation. Assume as a starting point that the inductance value of the down converter is 2.2 μH, and the decoupling capacitance is 330 μF with 4 mΩ ESR. Therefore,

V_{in} = 12 V

V_{out} = 1.5 V

L = 2.2 μH

C = 330 μF

R_{esr} = 5 mΩ

I_{i} 0.5 A

I_{2} = 8.5 A

Applying above parameters into Equation 4 and Equation 7 shows that after the beginning of a 0.5 A to 8.5 A loading transient, at t=0.36 μsec., the maximum voltage drop of 32.9 mV occurs on the output capacitor array.

After the beginning of a 8.5A to 0.5 A unloading transient, at t=10.4 μsec., the maximum voltage rise of 144.0 mV occurs on the output-capacitor array.

A spreadsheet should be used for these calculations, and further calculations show that the ESR dominates the voltage drop in loading transients, and the capacitance dominates the voltage rise in unloading transients.

Repeated calculation trials show that C=720 μF and R_{esr}=6.2 mΩ are the optimum values to meet the 1.5 V ± 75 mV voltage window

Ceramic capacitors have low ESR and small capacitance. However, the low ESR effect of ceramic capacitors is only valid for the duration that ceramic capacitors can hold energy, calculated by C(dv/dt)=I. Electrolytic capacitors have high ESR and large capacitance. However, the high capacitance effect of electrolytic capacitors kicks in only after the resonance time, calculated by R_{esr}C. Polymer tantalum capacitors lie somewhere in the middle, and have relatively low ESR and relatively high capacitance.

What can be used to make up the resultant 720 μF capacitance and 6.2 mΩ ESR? Two 330 μF, 30 mΩ (ESR) polymer tantalum capacitors, and six 10 μF, 2 mΩ (ESR) ceramic capacitors can configure capacitor arrays. Capacitor arrays should be placed from the load in descending order of their resonance frequencies. Ceramic capacitors have the highest resonance frequency, so they should be placed closest to the load, polymer tantalum capacitors next closest, and electrolyte capacitors furthest from the load.

Equation 4 and Equation 7 also imply that a smaller inductance is better for reducing voltage excursions. Reducing the inductance from 2.2 μH to 1.2 μH will cut down the capacitance value from 720 μF to 390 μF. The inductance value is an important element for a voltage-down converter, and should be considered to integrate efficiency optimization, inductor ripple current, and output-capacitance array-calculation process.

**About the author**

** Takashi Kanamori** is an Applications Engineer at Summit Microelectronics, www.summitmicro.com. He has 10 years of experience in the industry, holding a Master's degree from California Institute of Technology, where he specialized in Power Electronics. Prior to joining Summit Microelectronics, he was in charge of designing power delivery architecture for portables, desktops, and servers in Apple, Inc. He also worked as a technical staff in Lucent Technologies, where he worked on isolated power bricks for telecommunication.