(Editor's Note: There are links to the previous parts of this series at the end, below the author's biography.)
In December 2007, Part 4 and Part 5 of this column introduced the concept of analog-to-digital conversion and introduced the four major converter topologies. In all cases, an analog-to-digital converter (ADC) determines a digital approximation of an analog voltage by comparing it to a reference.
In this part, we'll examine flash and pipeline converters. We'll discuss successive-approximation and sigma-delta devices in Part 9.
The flash converter in Figure 1 is perhaps the simplest topology:
Figure 1: 3-bit flash ADC
An N-bit flash converter is composed of 2N-1 converters, 2N resistors, and a logic network to sort the results into the binary code. In this configuration, Vref is equal to the converter full-scale voltage.
The resistor string values are such that the voltage at the inverting input of comparator one (COMP1) is a one-half LSB. The rest of the resistor steps are one LSB, so the inverting input of COMP2 is one-and-a-half LSBs.
- When Vin < ½="" lsb,="" then="" all="" outputs="" are="">
- When ½ LSB < vin="">< 1½="" lsb,="" then="" comp1="HI">
- When 1½ LSB < vin="">< 2½="" lsb,="">
then COMP1 and COMP2 = HI
As the magnitude of Vin increases, the number of comparator outputs that are high increases. It is the job of the binary conversion logic to change this series of comparator outputs into the respective binary code.
The flash converter has the advantage of speed. Limiting factors are propagation times of the comparators and logic network. Disadvantages are in the number of precision resistors (2N) and comparators (2N-1) required. An 8-bit converter requires 255 comparators.
Consider the pipeline converter as a series string of 1-bit flash converters, Figure 2
Figure 1: Simplified pipeline converter
(Click on image to enlarge)
The pipeline converter is a clocked topology where every action happens on a clock timing cycle. On the first clock, the applied signal, Vin, is captured in a sample-and-hold block (S/H1). This voltage (V1) is applied to comparator B1. If V1< vref,="" then="" sw1a="" is="" closed,="">1 is amplified by two, and the result is applied to the next stage. If V1> Vref, then SW1B is closed, the value (V1 - Vref) is amplified by two, and that result is applied to the next stage.
When SW1A is closed, a binary zero is recorded for the most significant bit (MSB). This is because the applied voltage is less than one-half the full-scale voltage (Vfs/2). When SW1B is closed, a binary one is recorded for the MSB because the applied voltage is greater than Vfs/2. On the next clock cycle, this process is repeated at the second stage to determine the value of MSB - 1.
The following numerical example helps to illustrate the action:
- If Vfs = 5.0V, then Vref = 2.5V.
When Vin = 3.70V, V1 = 3.70V.
- Since V1 > Vref, SW1B is closed and MSB = 1
- The input to the first amplifier is 3.7 - 2.5 = 1.2V,
and V2 = 2 × 1.2 = 2.4 V
- Since V2 < vref="" ,="" sw2a="" is="" closed="" and="" msb="" -="" 1="">
Since the first stage is now vacant, it will process the next analog-input value. A complete conversion for an N-bit result requires N clock cycles. However, the time between results is just one clock cycle. The time lag between an event in the analog input and the result showing at the digital output
will be N clock cycles. This is termed data latency
(In the next installment, we will discuss the successive-approximation (SAR) and delta-sigma topologies.)
About the author
William P. (Bill) Klein is a Senior Applications Engineer with the High Performance Analog group at Texas Instruments. Bill joined TI through its acquisition of Burr-Brown in August 2000. His experience as an analog circuit designer covers over 40 years in fields ranging from mineral exploration to medical nuclear imaging. One current role Bill has is hosting the Analog e-LAB Web Cast, presenting real world solutions to real world problems in analog circuit design. In addition to a BSEE from Arizona State University and registration as a Professional Engineer in the State of Arizona, he has authored numerous magazine articles, application notes and conference papers.
Previous installments of this series:
- "SIGNAL CHAIN BASIC Series (Part 7): Op Amp Performance Specification--Bias Current", www.planetanalog.com/features/showArticle.jhtml;?articleID=206101908, click here
- "SIGNAL CHAIN BASIC Series (Part 6): Op Amp Input Voltage Offset", www.planetanalog.com/features/showArticle.jhtml;?articleID=205901111, click here
- "SIGNAL CHAIN BASICS Series (Part 5): Introduction to the Instrumentation Amplifier", www.planetanalog.com/features/showArticle.jhtml;?articleID=205208593, click here
- "SIGNAL CHAIN BASICS Series (Part 4): Introduction to analog/digital converter (ADC) types", www.planetanalog.com/features/showArticle.jhtml;?articleID=204803631, click here
- "SIGNAL CHAIN BASICS Series (Part 3): Analog and the digital world", www.planetanalog.com/features/showArticle.jhtml;?articleID=204400376, click here
- "SIGNAL CHAIN BASICS Series (Part 2): Op Amp--Basic operations", www.planetanalog.com/features/showArticle.jhtml;?articleID=203101699, click here
- "SIGNAL CHAIN BASICS: Operational Amplifier--The Basic Building Block", www.planetanalog.com/features/showArticle.jhtml;?articleID=202801320, click here