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Understanding the effect of clock jitter on high-speed ADCs (Part 1 of 2)

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re: Understanding the effect of clock jitter on high-speed ADCs (Part 1 of 2)
TEJDMAXIM   9/23/2008 6:39:26 PM
I read Part I of your article, and while it highlights the ADCproduct, it does not provide any information about jitter that had not already been published a quarter-century ago, by others, with the exception of its statement that compares jitter noise produced by a uniform band of frequencies, compared to the noise induced by jitter on a single tone: "For a simplistic example, a uniform band of power from DC to 1 MHz is 6 dB less sensitive than a single tone, or a narrow band, with equivalent power at 1 MHz..," I may be wrong, but I believe that statement is incorrect, and if I understand "reduced sensitivity" to be reduction in jitter-induced noise, that noise is lower by 4.77 dB (1/3 less power), not by the stated 6 dB (1/4 less power).

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