Breaking News
Design How-To

SIGNAL CHAIN BASICS (Part 31): Digital interfaces (con't) -- The SPI Bus

More Related Links
View Comments: Newest First | Oldest First | Threaded View
User Rank
re: SIGNAL CHAIN BASICS (Part 31): Digital interfaces (con't) -- The SPI Bus
dwieberd   7/17/2009 9:13:52 PM
Assuming there is data for more than one address being transmitted; for the case of a single slave, I think you would still need to use the slave select to keep the slave's address counter synchronized with the master's; ie. it needs to be pulsed active to signify when the data sequence is starting over.

August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
Top Comments of the Week
Like Us on Facebook Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.