The second step is to design the output filter. The switching frequency will determine the filter corner frequency. In this case, a switching frequency of 140 kHz is chosen. This frequency is high enough to significantly reduce the size of the output filter, while low enough to limit switching losses. A fourth order output filter is chosen to achieve a sharp frequency roll off. The characteristic filter impedance is directly related to the speaker impedance, with additional damping required through a Zobel network to improve response for higher impedance speaker loads.
However, since the subwoofer bandwidth is significantly lower than the filter bandwidth, the filter requirements in this case are relaxed. The resultant Bode plot for the output filter (Figure 6b, third image below) is shown in Figure 2, immediately below. To avoid saturation under normal operation, all filter inductors should be current rated in excess of the peak current value calculated in Equation 2, in this case 23A.
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Gate drive design and propagation delay variation
In general, switching timing error in the gate drive signal is the primary cause of the non linearity for a Class D amplifier. The timing error due mismatches in signal propagation causes variation in the dead-timethe most significant contribution of nonlinearity in a Class D stage. A small amount increase in the dead time (tens of nano-seconds) can easily generate more than 1% of THD [Reference 1].
On the other hand, if the dead time is decreased beyond a certain point (depending on the switching speed of the MOSFETS), then both devices are conducting at the same timewhich leads to large shoot-through currents that can, at the very least, reduce efficiency and, worse, result in device destruction. The minimum amount of dead time that can be set in production will depend on the worst case mismatch on the propagation delays between the two gate drive signals from the point where the control signal splits (considering component tolerances and part-to-part variation). Add to this the fact that the total gate charge (for the three devices in parallel) is over 240 nC, thus requiring a high (sink/source) current gate drive with accurate timing.
Furthermore, a floating (isolated) gate drive (both supply and control signal) is required for the top MOSFET (high side). Thus the high-side gate drive signal propagation has to be matched with that of the low side (where no isolation is needed). The IR2010S gate drive IC is selected at it matches these vital requirements:
Delay matching of outputs to within 15 ns
A 3A sink/source current capability
Floating high side output for up to 200V isolation
(For more complete information of gate drive ICs refer to Application Note AN-978 [Reference 3].)
The IR2010S is a high-and low-side driver with separate logic input for each of the two gate drivers (HO and LO) and requires external dead time creation. This is done through a simple edge dependent RC delay circuit as shown in the final design schematic, Fig. 6a immediately below.
Figure 6a shows the Class D subwoofer gate drive and protection circuits.
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Figure 6b shows the Class D subwoofer output stage.
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The high side gate drive needs a bootstrap power supply. A bootstrap supply is implemented simply by adding a diode between the low-side and high-side supplies. The high-side bus capacitance is recharged every time the low side MOSFET is on, while the floating bus capacitor must supply the high side current during high side MOSFET conduction. The size of this bus capacitor is, therefore, determined by the total maximum on-time of the high-side MOSFET and the allowable voltage ripple on the capacitor. The worst case would be during clipping of the output voltage when the output is over-modulated (such as at 10% THD). For a low frequency fundamental, this on-time could be tens of milliseconds, resulting in the need for a large (100 μF) bus capacitor. (Please refer to Reference 3 for more on bootstrap supply design.)
With the gate drive selected, the heart of the Class D amplifier is complete. At the input side is a PWM logic signal, while at the output, this signal is amplified into a large PWM modulated square wave voltage, where the carrier frequency is filtered out. The final step is to create a control loop with feedback and compensation to connect the output of the preamp to the Class D amplifier. Lastly, the control loop output has to be "quantized" to generate the required PWM signal (see Figure 1).
Pre amplifier design
This falls outside the scope of the Class D amplifier design, but is noteworthy. As it is easier to achieve voltage gain with good THD performance in the preamp than in the class D power stage, it is advisable to limit the voltage gain of the power stage by increasing the preamp gain.