Developing Analytical Equations for Determining Power MOSFET Switching Transients
This article explains the switching behavior of power MOSFETs in practical application circuits and shows the reader/designer how to choose the right device for the application using the specifications typically provided on manufacturer datasheets. The article goes through several methods of assessing the switching performance of power MOSFETs and compares these against practical results. The comparison shows that datasheet values can be used to obtain a reasonable indication of the switching performance of a MOSFET as well as its switching losses, but calculated switching transients will always be shorter than those actually achieved. Therefore, maximum parameters from the datasheet should always be used to give realistic results.
Switching the MOSFET in isolation
Using capacitance
To get a fundamental understanding of the switching behavior of a MOSFET, it is best first to consider the device in isolation and without any external influences. Under these conditions, an equivalent circuit of the MOSFET gate is illustrated in Figure 1, where the gate consists of an internal gate resistance (R_{g}), and two input capacitors, (C_{gs} and C_{gd}). With this simple equivalent circuit it is possible to obtain the output voltage response for a step gate voltage.
Figure 1. An equivalent MOSFET gate circuit showing just C_{gs}, C_{gd} and R_{g}
The voltage V_{GS} is the actual voltage at the gate of the device, and it is this point that should be considered when analyzing the switching behavior of the device.
If a step input is applied at V_{GS_APP}, then the following holds true:
(1)
(2)
(3)
and since VDS is fixed
(4)
therefore:
(5)
and
(6)
giving
(7)
(8)
@t=0, V_{GS} =0, therefore
(9)
This gives an indication of how long the actual gate voltage (V_{GS}) takes to get to the threshold voltage.
When the MOSFET is considered with additional parasitics, it becomes increasingly difficult to manipulate these equations manually for such a practical circuit. If these secondorder, or parasitic, components are ignored, then it is possible to come up with formulas for the turnon and turnoff time periods of the MOSFET. These are given in Equations 10 through to 15 and the resulting waveforms are shown in Figures 2 and 3. These equations are based on those developed by B J Baliga^{[1]}, where R_{G} is the internal gate resistance, R_{G_APP} is the external gate resistance, V_{th} is the MOSFET threshold voltage, and V_{Gp} is the gate plateau voltage.
[10]
[11]
[12]
VF is the voltage across the MOSFET when conducting full load current and VDS is the voltage across the MOSFET when it is off.
This gives an accurate t1 and t2 when using datasheet values, but the time period t3 is difficult to calculate since Cgd changes with VDS.
Figure 2. Turnon transient of the MOSFET
Using the same principles for turnoff, the formulas for the switching transients are given below:
[13]
[14]
[15]
In this instance, t_{4} and t_{6} can be calculated accurately, but it is the formula for t_{5} which is more difficult to solve, since during this time period V_{DS} will change, causing C_{gs} to also change. Therefore some method is required to calculate t_{3} and t_{5} without using the dynamic C_{gd}.
Figure 3. Turnoff transient of the MOSFET
Using gate charge to determine switching time
Looking at the gate charge waveform^{[2]} in Figure 4, Q_{gs} is defined as the charge from the origin to the start of the Miller Plateau (V_{GP}); Q_{gd} is defined as the charge from V_{GP} to the end of the plateau; and Q_{g} is defined as the charge from the origin to the point on the curve at which the driving voltage V_{GS} equals the actual gate voltage of the device.
Figure 4. Sketch showing breakdown of gate charge
The rise in V_{GS} during t_{2} (Figure 2) is brought about by charging C_{gs} and C_{gd}. During this time V_{DS} does not change and as such C_{gd} and C_{ds} stay relatively constant, since they vary as a function of V_{DS}. At this time C_{gs} is generally larger than C_{gd} and therefore the majority of drive current flows into C_{gs} rather than into C_{gd}. This current, through C_{gd} and C_{ds}, depends on the time derivative of the product of the capacitance and its voltage. The gate charge can therefore be assumed to be Q_{gs}.
The next part of the waveform is the Miller Plateau. It is generally accepted that the point at which the gate charge figure goes into the plateau region coincides with the peak value of the peak current. However, the knee in the gate charge actually depends on the product^{1} (C_{gd}V_{GD}) with respect to time. This means if there is a small value of drain current and large value of output impedance, then IDS can actually reach its maximum value after the left knee occurs. However, it can be assumed that the maximum value of the current will be close to this knee point and throughout this application note it is assumed that the gate voltage at the knee point corresponds to the load current, I_{DS}.
The slope of the Miller Plateau is generally shown to have a zero, or a nearzero slope, but this gradient depends on the division of drive current between C_{gd} and C_{gs}. If the slope is nonzero then some of the drive current is flowing into C_{gs}. If the slope is zero then all the drive current is flowing into C_{gd}. This happens if the C_{gd} V_{GD} product increases very quickly and all the drive current is being used to accommodate the change in voltage across C_{gd}. As such, Q_{gd} is the charge injected into the gate during the time the device is in the Miller Plateau.
It should be noted that once the plateau is finished (when V_{DS} reaches its onstate value), C_{gd} becomes constant again and the bulk of the current flows into C_{gs} again. The gradient is not as steep as it was in the first period (t_{2}), because C_{gd} is much larger and closer in magnitude to that of C_{gs}.
Combination of gate charge and capacitance to obtain switching times
The objective of this note is to use datasheet values to predict the switching times of the MOSFET and hence allow the estimation of switching losses. Since it is the time from the end of t_{1} to the end of t_{3} that causes the turnon loss, it is necessary to obtain this time (Figure 2). Combining 10 and 11 it is possible to obtain the rise time of the current (t_{ir}=t_{2}t_{1}) and because V_{DS} stays constant during this time then it is possible to use the specified datasheet value of C_{iss} at the appropriate V_{DS} value. Assuming the transfer characteristic is constant, then V_{GP} can be substituted for V_{th} + I_{DS/gfs}, hence:
[16]
It is difficult to use a value of C_{gd} for the fall time period of V_{DS} (t_{vf}=t_{3}). Therefore if the data sheet value of gate charge is used (Q_{gd_d}) and divided by the voltage swing seen on the drain connection (V_{DS_D} minus V_{F_D}) then this effectively gives a value for C_{gd} based on the datasheet transient.
[17]
Similarly for the turnoff transition, the voltage rise time (t_{vr}=t_{5}) is:
[18]
and the current fall time (t_{if}=t_{6}) is:
[19]
Comparing equations with datasheet values
The definition of the turnon and turnoff times given in the datasheet can be seen in Figure 5. These definitions can be equated to the equations described above and are shown here:
[20]
[21]
[22]
[23]
Figure 5. Sketch showing definition of turnon and turnoff times

Table 1. Worked example for switching transients: Si4892DY
The minimum switching transients were calculated using the appropriate value of the parameters, which resulted in producing the shortest switching transient value. In some circumstances this meant that the maximum value of a parameter was used to calculate the minimum switching transient and vice versa for the maximum switching transients.
Comparing equations with measured switching transients
The datasheet switching transients are measured with a resistive load and are not truly representative of a practical circuit. As such the device will not behave according to the ideal operation described above. Therefore, actual switching waveforms were measured, and these are shown in Figures 6 and 7. These switching transients are for the Si4892DY implemented on the high side of a buck converter configuration. The circuit parameters were:
VDS = 5V, IDS = 5 A, VGS_APP = 5 V, and Rg_app = 10Ω
Figure 6. Measured current and voltage turnon switching transient
Figure 7. Measured current and voltage turnoff switching transient

Table 2. Measured versus calculated
Limitations of the driving circuit
Table 2 shows the comparison between the calculations and the measured transients. It can be seen that the voltage transients are relatively close. However, the switching times of the MOSFET are affected not only by the parasitic elements, but also by the driving circuit. Under the conditions described above, the author has assumed that the gate circuit does not limit the switching performance of the power MOSFET. For example, with a MOSFET pchannel and nchannel driver, it is possible that the theoretical current into the gate will be larger than that which the driver is able to supply. There are several ways in which a MOSFET driver can be realized and this goes beyond the study of this application note. The formulas described in the text are used to gauge the switching times and therefore estimate the switching losses without navigating complex formulas, models and expensive simulation software.
The major discrepancy is between the calculated and actual current transients. These calculations are an order of magnitude less than the actual transients. Therefore, further consideration has to be taken for the current rise and fall times and this is described below.
Current transients
The discrepancy between the calculated and the measured occurs because the calculations assume an ideal situation. One major parameter that can be considered into the equations is the package inductance of the MOSFET. This will slow the current transient and can be taken into account with relative ease if a few assumptions are made.
Since the load current will generally be much larger than the gate current, it is assumed that all the current through the package inductance will be IDS. Therefore it can be shown that the voltage across the package inductance of the MOSFET during turnon will be:
[24]
This is the voltage that occurs from the current transient and as such subtracts from the gate voltage and hence slows down the current transient. If Equation 24 is subtracted from VGS and solved for t, the tir transient is:
[25]
Applying the same principle for tif results in a current transient as follows:
[26]

Table 3. Measured versus calculated with package inductance
Conclusion
The rise and fall times for power MOSFETs can be approximated with relative ease when evaluated in isolation. By plugging in datasheet values into the formulas derived above, we can get a reasonable indication of the switching performance of the MOSFET as well as the switching losses. However, since second order parasitics are not included the analytical equations will always be shorter than those actually achieved. Hence the maximum parameters from the datasheet should always be used to give realistic results.
Author Information
Dr. Jess Brown is DC/DC Applications Manager at Vishay Siliconix. Before joining the company, he spent the previous eight years in power electronics research. His areas of expertise include switchmode power supply applications, brushless ac and dc threephase permanent magnet motor drives, and power loss measurements. In 2004, he delivered papers at Power Systems World (Chicago), PCIM Europe, and APEC. He holds a Bachelor of Engineering degree and a Doctor of Philosophy (Ph.D) in Power Electronics. He is a Chartered Member of the Institute of Electrical Engineers (MIEE, CEng).
References
[1]. B J Baliga, Power Semiconductor Devices.
[2]. Gate Charge Principles and Usage, Power Electronics Europe, Issue 3 2002, Technology