This article provides a detailed design and experimentation of a low cost, efficient (87%) isolated dc-dc converter that can be used in Powered Devices (PDs) of Power over Ethernet (PoE) applications in order to comply with the IEEE Standard 802.3af. Before discussion of the design, it is appropriate to present the context in which this design will be used.
The IEEE Standard 802.3af was ratified in June 2003, it defines the specifications and protocols for distribution of low power (<15.4w) at="" low="" voltage="" (-48vdc)="" over="" the="" standard="" existing="" ethernet="" cabling.="" over="" the="" next="" few="" years,="" poe="" is="" expected="" to="" become="" a="" standard="" feature="" on="" all="" high-end="" switches="" and="" routers.="" for="" example,="" applications="" such="" as="" voice="" over="" internet="" protocol="" (voip)="" and="" lan="" wireless="" are="" expected="" to="" grow="" to="" 18="" million="" units="" by="" 2007="" (source:="" isuppli).="" furthermore,="" poe="" would="" eliminate="" the="" need="" for="" many="" ac="" adaptors="" as="" well="" as="" ac="" ports="" in="" remote="" locations.="">15.4w)>
Power Source Equipment (PSE) is the device that provides the power source, and Powered Device (PD) is the network peripheral device at the other end of the cable that is able to accept the power.
In the example of Figure 1 the original Ethernet switches are PoE enabled by a 'midspan' Power over Ethernet hub, which will 'inject' the power into the twisted pair LAN cables. Newer Ethernet switches will incorporate the 'midspan', providing power to the Powered Devices (PDs) that are connected via high speed data cabling. These Powered Devices can be web cams, Voice over Internet Protocol telephones, Wireless LAN access points and other appliances. The Uninterruptible Power Supply (UPS) will provide back up power should the main power supply fail.
Figure 1. Midspan Hub retro-fitted to Ethernet Switch
Figure 2 shows a simplified block diagram of the input side of a PD, which includes the dc-dc converter.
Figure 2. Powered Device Block Diagram
The IEEE 802.3af Part 3: (CSMA/CD) Access Method and Physical Layer Specifications - Data Terminal Equipment - power via Media Dependent Interface, specifies the PSE and PD (input side) power supply power up sequence requirements.
Why Flyback converter
The Flyback topology has been traditionally the designer's choice for low power (below 50W) isolated converters. It requires only one magnetic component and one output rectifier, so it has the advantages of simplicity and low cost. Despite of that, high efficiencies can be achieved as proven by Ionel D. Jitaru, "High Efficiency Flyback Converter using Synchronous Rectification", 2002 IEEE.
The basic specifications of the present design for a Power Device are summarised in Table 1.
High efficiency in a low power converter is difficult to obtain due to the relatively high bias and control circuit power losses respect to the output power, which has a bigger impact during operation at low loads. In our case, the problem is worse due to the added bias power lost in the interface circuit for PoE compliancy.
Table 1. PD Power Supply Basic Specifications
Careful specification/selection of the transformer and the switching MOSFET greatly contributes for low power losses. In addition, switching frequency reduction techniques at low load can be used to save power.
Figure 3. Schematic of the PD converter implemented
Figure 3 represents the schematic of the converter designed. It consists of an interface, an input LC filter, start-up and bias circuits, power section and control stage. This is a generic design that meets the power requirements of the IEEE 802.3af standard. However, it would need additional combined components such as the input sockets connectors, transmission transformers input rectifiers and EMC filter for fully compliance with international standards.
Interface to comply with the IEEE standard 802.3.af
When a PD is plugged in a PoE system, there are three distinctive phases that occurs in sequence; these are detection, classification and power turn-on, which also should comply with certain timing.
During the detection phase, the PSE determines whether or not a PD has been connected. The detection criteria by which a PSE shall accept as a valid signature, is a signature resistance Rgood
The detection resistance used is 24K9, which is within the PD detection range. In order to save power losses, we disconnect this resistor when input voltage is above 30V, this way, we can save about 85mW of power. This is be done by using the same comparator circuit that turns on or off the series switch MOSFET Q1 for power up of the converter.
Classification: Class 0, or the class by default, which can operate at the maximum power (or 12.95W) at the input of the dc-dc converter The interface doesn't need to provide any additional information to the PSE, so circuit is simplified.
Power turn on circuit: The PSE supplies a minimum of 44V, however in order to account for the losses in the Ethernet cabling, connectors, transmission lines transformers and rectifiers, the PD power supply should work from a minimum of 36V. This circuit isolates the PD from the PSE during the detection/ classification stages. Effectively this is an under voltage lockout which turns on the MOSFET Q1 when the input voltage is above 30V. It also limits the inrush current, although this is not a requirement for a PD if this has less than 180μF input capacitance.
Figure 4 shows the power turn on event. When 48V is applied, there is an initial inrush current due to the input 100nF EMC, note that standard IEEE 802.3af allows the insertion of this capacitor. This current spike however will be damped due to the impedance of the Ethernet cabling. After 7mS the MOSFET Q1 starts to limit the inrush current, which charges the Flyback decoupling capacitors C8, C13 and C18. This inrush current is limited to 365 mA by slowly increasing the gate voltage of MOSFET Q1 via resistor R11 and capacitor C22.
Figure 4. Power turn on waveforms from 48Vin
Ch3(Red)=Voltage across On/Off switch Q1,
Ch2(Green)=Current in Q1,
M1(Pink)=Power in Q1
In Figure 5 we can see the monotonic output voltage start-up sequence after 48Vdc input is applied. During this test, the output load is set to the maximum current of 2.2A.
Figure 5. Output Soft Start after Power up from 48Vin.
After power is finally released from the PSE, the regulator formed by R21 and Q5 provides the initial input voltage for the control circuit, the current charges the PWM IC decoupling capacitors until its UVLO level is reached and the PWM starts switching.
Once it starts switching, the voltage developed via the auxiliary winding reduces the Vgs voltage of MOSFET Q5 until it turns off. This stops current from flowing through the bleeding resistor and consequently saving some power losses.
PWM Start-Up and Soft Start function
The IC PWM controller will activate the converter as soon as the voltage on pin VCC reaches the VCC (start) level of 11V. Below the start-up level, the IC under-voltage lockout disables most of the internal circuitry, consuming less than 70μA.
To prevent transformer rattle during hiccup, the transformer peak current is slowly increased by the soft start function. This can be achieved by inserting a resistor and a capacitor between pin Isense and the sense resistor, see Figure 3. An internal current source charges the capacitor to V=ISSxRSS, with a maximum of approximately 0.5 V. The start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of R17 and C15.
The charging current ISS will flow as long as the voltage on pin Isense is below approximately 0.5V. If the voltage on pin Isense exceeds 0.5 V, the soft start current source will start limiting the current ISS.
The transformer in a Flyback converter is probably the most critical part of the design. The first decision to make is about the maximum operating duty cycle we allow (in this case less than 50%), this will give us the transformer ratio required. Secondly, we select the transformer magnetising inductance in order to achieve continuous conduction for most of the load. As a consequence of those designed parameters, we obtain a combination of currents in primary and secondary sides, which gives the optimum operating point or 'sweet spot' where the losses are the lowest.
The widely used EFD20 (Economic Flat Design) core shape provides significant advantages for miniaturisation of the power supply. This offers significant reduction in transformer core height, together with efficient use of volume and low cost. The core material 3F3 from Ferroxcube gives good performance for frequencies up to 500kHz. The surface mounted coil-former uses U-pins rather than the typical "gull-wing", which is more susceptible to co-planarity degradation due to tensions introduced by the winding wires. For more information see "Magnetics Design" Philips Semiconductor Applications. 1995. The final specifications of the transformer includes an EFD20/AL250 ferrite core, and windings with Np=26, Np1=18 and Ns=8. Although there are some of-the-shelf Flyback transformers in the magnetics market, in order to optimise the design, it is necessary to make a custom component. For this current design, Pulse has provided the custom parts.
Power supply designers are well aware of how much the leakage inductance contributes to additional power losses and increase of the voltage spike at the drain of switching MOSFET.
Ip_peak is the peak current in primary
Lm is the transformer magnetizing inductance
Ll is the transformer leakage inductance
Cds is the total capacitance at the drain of the primary MOSFET
Fs is the switching frequency
Therefore, this leakage inductance should be minimised. The technique used in this case to reduce the leakage inductance is interleaving with split of the primary winding in two halves.
The control section includes the Philips TEA1506 PWM controller IC and the feedback compensation circuit.
Current mode control is used for its good line regulation behavior. The internally inverted control voltage adjusts the on-time, which is compared with the primary current information. The primary current is sensed across an external resistor (R7, R14 and R15 in parallel). The driver output is latched in the logic, preventing multiple switch-on.
The GreenChip II (1) is the second generation of green Switched Mode Power Supply (SMPS) control ICs. A high level of integration leads to a cost effective power supply with a low number of external components. This PWM controller IC was selected based on its low cost and simplicity of use because it requires a minimum amount of external components. Since it is used in an isolated converter, the IC doesn't require the error amplifier inside.
The special built-in green functions allow the efficiency to be optimum at all power levels. When the IC is configured for operation in continuous conduction mode, the controller operates in fixed frequency mode (175kHz) at high and medium power levels. When the output load drops, the controller will smoothly change to discontinuous mode; the design of the transformer, actual input voltage and current sense resistor determines the crossover point. As output power reduces, the frequency is continuously controlled down, the controller runs at the minimum on-time, and the output power is controlled by varying the switching frequency down to a minimum frequency of approximately 25 kHz, therefore reducing the power losses. At even lower power level, if the voltage on the control pin rises even more, the IC activates a cycle skipping mode and inhibits the switch-on of the external power MOSFET until the voltage on the control pin has dropped to a lower value again.
Over-Current Protection (OCP): The cycle-by-cycle peak drain current limit circuit uses the external source resistor to measure the current accurately. The circuit is activated after the leading edge blanking time that provides current sense noise immunity. The OCP circuit limits the 'sense' voltage to an internal level.
Over-Temperature Protection (OTP): An accurate temperature protection is provided in the circuit. When the junction temperature exceeds the thermal shutdown temperature, the IC will enter the safe restart mode. When the Vstart level is reached, switching starts again. This process is repeated as long as the OTP condition exists.
The presence of the right half-plane (RHP) zero in the loop is always a potential problem with a Flyback operating in CCM. The literature, for example (Lloyd H. Dixon "The Right-Half-Plane zero. A simplified explanation". Unitrode Seminar 1984.), recommends to set up the cross over frequency (fc) very well below the RHP zero frequency, at least a decade should guarantee stability, although it would penalize the load transients response.
Where Rl is the output load resistance
Slope compensation is normally recommended for peak current mode control when duty cycle is above 50%; however in this design, the estimated maximum duty cycle at minimum input voltage is 44% and therefore ramp compensation was not considered necessary.
Is not the objective of this work to present a complete small signal analysis of the loop compensation. The best practical approach is to use spice modelization due to the complexity in finding the right mathematical expression for the optocoupler and shunt regulator frequency response characteristics. This is still a topic of continuous research interest, more information can be found for instance in:
1. Yuri Panov and Milan Jovanovic. "Small-Signal Analysis and Control Design of Isolated Power Supplies with Optocoupler Feedback". APEC'04
2. R. Kollman, J. Betten, "Closing the Loop with a popular Shunt Regulator" Power Electronics Technology Magazine, pp. 30-36, Sep, 2003.
For highest efficiency and ease of driving, the obvious solution is an N-Channel MOSFET driven directly from the output pin of the PWM IC as this is capable without the use of an external driver. The selection of the MOSFET is based on a compromise between switching and conduction losses in order to minimize the total. The MOSFET used in this occasion is the Philips PHK4NQ20T in SO8 package with the basic characteristics as in Table 2.
Table 2. Switching MOSFET characteristics
MOSFET losses can be estimated as:
Ip-valley is the valley current in the transformer primary
Ig_off is the driver sink current
Ig_on is the driver source current
Fs is the switching frequency
Vdc is the PWM IC driver voltage
Figure 6 shows the continuous mode of operation at 48Vin and full load. Also note the small voltage spike and ringing at the drain of the switching MOSFET despite not using any snubber. This solution provides additional reduction in power losses (no dissipation in snubber) and simplicity of design since there is no need for designers to calculate and select a snubber.
Figure 6. Switching waveforms in primary side
Ch3(Red)=MOSFET Gate voltage,
Ch1(Black)=MOSFET Drain to ground voltage
Ch2(Green)=MOSFET Source current (433mA/div)
The current waveform of Figure 6 is taken as a voltage developed across the current sense resistors.
Note that during MOSFET turn-off, the voltage measured across the current sense resistors shows an abnormal shape. This reduction in current is due to the subtraction caused by the MOSFET gate discharge current. Similarly happens during the turn on, where the waveform includes the gate charging current.
As it can be seen from the figures 7 and 8, the switching transitions are quite fast, about 15ns for the MOSFET turn off and 25ns for the turn on. There is a significant discrepancy between the estimated turn on transition time (65nS) and the actual one; this is due to the lower driver source current and higher Qgd used in the calculations. Current waveform (green trace) shows that the actual driver current is about 260mA, at least before the gate threshold voltage is reached.
Figure 7. Switching waveforms in primary side. Turn On detail
Ch3(Red)= MOSFET Gate voltage
Ch1(Black= MOSFET Drain to ground voltage
Ch2(Green)= Source current (433mA/div)
Figure 8. Switching waveforms in primary side. Turn Off detail
Ch3(Red): MOSFET Gate voltage
Ch1(Black): Drain to ground voltage
Ch2(Green): Source current (433mA/div)
The best obvious solution is a Schottky rectifier for its low switching and conduction losses. The selected part for this design was the Shindengen DE10DP3, which offers under 0.3V forward voltage at 2.2A of current in a DPAK for easy cooling and low temperature rise.
Output Filter Capacitors
An advantage of the continuous conduction is that it requires less output capacitor ESR that in the discontinuous conduction mode, although load transient response is sacrificed with the larger magnetizing inductance.
The combination of an electrolytic capacitor (high capacitance value and low cost) with ceramic capacitors (low ESR and relatively low cost), offers the best design tradeoff. This way, the low ESR ceramic capacitors will handle the ripple current and won't cause any additional temperature rise in the electrolytic capacitor, which therefore will run reliably. The higher value electrolytic capacitor will help in the loop stability and will provide bulk energy needed during load transient response. This combination provides a lower cost solution than Tantalums, specialty polymers or two stage filters typically used in this application.
The output voltage ripple is mainly determined by the output capacitors ESR:
Figure 9 shows the typical output voltage ripple obtained, about 80mV peak-to-peak at nominal input voltage and maximum load should suffice for a typical 5V load.
Figure 9. Output voltage ripple at 48Vin, Io=2.2A
Estimated Total Power Losses
Theoretical power losses estimation indicates that 86% efficiency could be achieved. It can be seen in the Figure 10 that the control losses alone would represent about 28% of the total power wasted. This is mainly due to the dissipation in the current sense resistor. If we reduce it, for example by using a current sense transformer instead of resistors, the efficiency would improve nearly 2%. Also can be noted that the output rectifier represents the single item with most losses, this could be further improved by using synchronous rectification, although it would add complexity to the circuit. This is an option to be reconsidered again if the output current requirement increases.
Figure 10. Estimated power losses break down
Figure 11. Photo of fully assembled prototype
All components are surface mounted except the input/output pins and the test points. It was made in a standard FR4 PCB with two layers of 1oz copper thickness. All power components are on the topside of the board; the bottom side contains most of the control circuitry.
Note from Figure 12 the very high efficiency obtained at low loads as well, in particular at no load, with only 110mW losses thanks to the frequency reduction and pulse skipping techniques. The results are better than the previous estimation; the discrepancy is mostly due to the pessimistic MOSFET losses prediction. The converter achieves similar efficiency at lower and higher input voltages.
Figure 12 Measured Efficiencies of the implemented converter at 48Vin.
Checking the Stability -- Measured Bode Plots
Figures 13 and 14 confirm that the total system is stable and with significant phase margin under all possible conditions.
Figure 13. Measured Bode Plots at 48Vin, 0.1A
Figure 14. Measured Bode Plots at 48Vin,2.2A
Careful selection of the components allows the creation of a dc-dc converter for PoE Power Devices that at the same offers the advantages of simplicity and low cost, with the added benefits of being compact and high efficient.
(1) GreenChip is a trademark of Koninklijke Philips Electronics N.V.
Victor Guijarro is an applications engineer in the Power Management
Business Line of Philips Semiconductors. Guijarro has seven years of design experience in switch mode power
supplies in the electronics field. During his time at Philips he's also published a whitepaper on Power over Ethernet and completed a reference design of a Power over Ethernet-powered device. Guijarro holds two MOSFET driver-related patents. Guijarro earned his master's degree in electronics and control.