The monolithic high-side drive poses a fascinating challenge for system designers. Simply put, designers need to find a way to drive the switching devices as easily as possible -- without suffering from lack of speed or, wasting a large device area -- while maintaining low-voltage control capability. Additionally, they must do this using only the outputs of a micro controller or any other control circuits working in the 3.3V or 5V supply.
This article describes a high-voltage process for the high-side gate driver IC and the conventional high-side driver topology, and also addresses the driver IC problems. Additionally, it briefly explains a new proposed circuit technique that solves common challenges faced by designers of the conventional high-side gate driver IC, such as the critical malfunction of the high-voltage IC. Finally, in addition to explaining how to solve such a malfunction, the robustness issue will be explored through the design and some experimental results will be presented.
High Voltage Junction Terminated Process
It is difficult, and not area-effective to the design, to make every device in the high-side gate driver circuit endure high voltage up to 600V. Actually, only few tens of volts are required to drive the gate of the power MOSFET and IGBT. Thus, the high-side driver itself does not require a full high-voltage range operation. The offset voltage of the high-side driver, however, must be guaranteed up to the maximum allowable voltage. To satisfy this high offset voltage constraint, the high-side circuit is incorporated in the cathode area of the high-voltage diode.
The high voltage diode of a device such as Fairchild's HDG4 625V rate high-voltage process is comprised by P-substrate, which has high resistivity, N-type buried layer and low doped N-type epitaxial layer. These layers are designed to meet the 625V break-down voltage requirement. To horizontally isolate this diode from other devices, some isolation layers are needed. Since the cathode of the diode is made of N-epitaxial layer, P-type isolation is required. Unfortunately, P-type isolation (PISO) layer cannot guarantee 625V isolation rate.
The HDG4 process uses additional high-voltage isolation (HVI) structure, which is based on the RESURF technique and N-epitaxial layer. Owing to the HVI structure, the PISO layer between high-side circuit region (the cathode of the high voltage diode) and the HVI structure is fully depleted and it is possible to prohibit a high electric field from forming in the PSIO layer. Of course, it is not an easy job to accomplish the high-voltage junction termination. This phenomenon depends on the N-buried layer concentration, on its location in the HVI, and on the depth and the resistivity of N-epitaxial layer.
Once this design difficulty is overcome, the process gives a good area-effective LDMOS. The HVI structure in this example can be the drain of the LDMOS, and the MOS channel can be implemented in the PISO layer. Since the drain of the LDMOS has the same structure with the HVI, LDMOS can be implemented without need for extra area. This is a dramatic leap of the modern high-side gate driver IC process since the conventional process requires an additional area for the LDMOS.
High-Side Driver Configuration
Figure 1 shows a conventional high-side gate driver circuit configuration. The conventional high-side gate driver IC typically is composed of following six parts:
Input detection logic
Edge pulse generator
Figure 1. Conventional high-side driver configuration
(From now on this article will refer to the high-side gate driver IC as the HVIC.) Before transferring the input signal to the high-side drive circuit, through the level shifter circuit by high-voltage LDMOSs with R1 and R2, the input detection circuit determines the input signal with the logic triggering levels, VIH and VIL. From this signal, two kinds of short pulses are generated by the edge pulse generation circuit with respect to the rising and falling edges. The high voltage LDMOSs converts these short-pulse voltage-signals to the current-signals, and R1 and R2; remaking short-pulse voltage-signals at the high-voltage region. The "reshapers," which are a type of a comparator with a given threshold level, amplify the signals to swing between VB and VS. These signals determine the state of the S-R latch. By virtue of the S-R latch, the low-side input command can be transferred to the high-side region with only edge information. Finally, the output driver composed by M1 and M2 drives an external high voltage power device with appropriate current driving capability.
High Dv/Dt Noise Warning
A pulsating noise, however, also affects the state of the S-R latch. High dv/dt noise, especially, is the most dangerous type for this kind of pulse driven HVIC. Assuming the parasitic capacitance, Cp, of the LDMOS seen at the drain is 2pF and a noise which has dv/dt of 50V/nsec is applied to the VS node. This noise is coupled to VB by the bootstrapping capacitor, CBOOT. For the LDMOS drain voltage to follow the fast changing VB voltage, Cp must be charged with large current. The current can be estimated using the following equation:
The charging peak current due to high dv/dt noise reaches 100mA. The large charging current makes enough voltage drop on R1 and R2 to abnormally trigger the S-R latch. If there is easy and effective method to remove this noise perfectly, that would be the best solution to make the HVIC free from the malfunction. However, it is impossible to suppress the noise to be coupled to the HVIC. Therefore, it is very challenging work to increase the immunity of the HVIC on the noise.
Allowable Negative Output Voltage
VB and VS are the highest and lowest voltage of the high-side driver, respectively. The voltage difference, VBS, is almost constant by the bootstrapping capacitor, CBOOT, and a bootstrapping technique. VS, however, depends on the half-bridge output, since VS is supposed to be connected to the source of the external MOSFET or the emitter of the external IGBT. An ideal HVIC must operate regardless of the VS voltage situation. For a real HVIC, however, VS heavily affects the operation. Some examples of the HVIC operation versus VB are depicted in Figure 2 as described in the following (A) and (B):
(A) VS > 0:
Figure 2. Allowable negative VS problem: (A) VS >0, and (B) VS <>
The reshaper has the threshold level, VTH. Thus, only when the level shifter's output swing is below this level, is the signal recognized by the reshaper. If Vs is higher than 0, the level shifter's output swings enough to touch VTH level. Consequently, there is no problem for normal HVIC's operation.
In this case, VS is negative. Accordingly, the absolute VB voltage is lower than case of (A). Therefore, the maximum output swing of the level shifter is limited within VB and ground and,as a result, the reshaper cannot catch the level shifter's output and the S-R latch state cannot be updated.
In the case (B), the allowable negative VS voltage is "VTH since the HVIC does not respond below this level.
This malfunction can be frequently observed in the real application since there are so many chances for the HVIC to drive inductive loads. Figure 3(A) is very familiar half-bridge circuit using HVIC (where FAN7382 is a HVIC, which has a low-side driving circuit as well). This circuit drives an inductive load, L, and also has a current-sensing resistor. The switching inputs are shown in Figure 3(B). When HIN is high, a high-side external power MOSFET, whose drain is connected to 600V line, is turned on and supplies current to the inductor load. Even if LIN is high, and the low-side MOS is turned on some times later, the current flows from ground level to the load. Accordingly, output voltage (VS) becomes negative. Furthermore, the sensing resistor makes the output into a deep negative voltage. Following this, HIN becomes high again. What is wanted from the HVIC is to make the output become high. The HVIC, however, misses the command if the allowable negative VS voltage is higher than "V, as depicted in the figure.
Figure 3. Allowable negative VS problem at Inductive Load Application:
(A) A typical half-bridge configuration, and (B) Command missing due to the lack of allowable negative VS
Proposed HVIC Circuit
Today there are two goals to achieve with the HVIC: (1) to enhance the noise immunity for the high dv/dt noise, and (2) to extend allowable negative VS voltage. To achieve these goals, a new reshaper circuit is proposed (as shown Figure 4.)As explained previously, the allowable negative VS limitation comes from the predetermined threshold level of the reshaper. It is needless to say that it is possible to increase that limitation by increasing VTH level. Such design, however, makes HVIC too sensitive to the noise.The output of the level shifter swings from VB to ground direction, whereas the conventional reshaper is operating in the VBS supply voltage. Accordingly, the detection of the level shifter's output by the reshaper is determined by the VB voltage level and VTH of the reshaper.In this new approach, a V/I (Voltage-to-Current) converter is used to detour around the VTH problem. The V/I converter converts the level shifter's outputs to the current information. Since the only role of this circuit is conversion, VTH is not considered. Next, an I/V converter reconstructs the voltage signal, which swings between VB and VS supply rails from the current outputs of the V/I converter. After these sequences, the amplified signal is sent to the S-R latch. Owing to the V/I converter, the allowable negative VS voltage is no longer governed by the threshold level, VTH, of the reshaper. As long as VB voltages are large enough to meet the requirement voltage for the V/I converter and to make the level shifter to work, HIN input is never lost.
Figure 4. Proposed reshaper configuration which provides a noise-canceling function and enhances allowable negative VS range
Another merit of V/I and I/V conversion is that it is easy to sense noise and to attach a noise canceling circuit. Because high dv/dt noise is added on to VB line via the CBOOT, noise is commonly applied to all the elements attached to the VB line. Thus, for the common-mode noise, which has high dv/dt, the V/I converter gives same outputs. Whereas, the V/I converter outputs are different from each other for normal operation, as only one of two LDMOSs operates at a normal level shifter operation. Thus, it is not difficult to determine whether the V/I converter output is due to noise or not. Once the noise canceller recognizes a common-mode noise intrusion, it absorbs the current outputs of the V/I converter.
Owing to its unique topology, Fairchild HVIC demonstrates good noise immunity against high dv/dt noise up to 50V/nsec and guarantees an extended negative operation. At VBS=VCC=15V, the proposed method satisfies approximately "10V operation. Figure 5 shows the micro-photos of two new HVICs also from Fairchild: the FAN7380 and FAN7382, which are designed using the HDG4 process.
In general, the HVIC drives high-voltage and high-current switching devices. Resulting high-voltage peaks, noise and EMI can cause the HVIC to malfunction, sometimes leading to destruction. Therefore, considering the actual usage of the HVIC, the robustness is the key issue.
To test the robustness of the designed HVIC, positively pulsating noise is added to VBS in series and negative pulse is applied to VB line using the HP8114A's pulse generator. During the test, VBS is constantly biased to 15V. The test was performed by changing the output of an HP8114A programmable pulse generator from 0V to 80V.
Figure 5. Micro-photo of the designed half-bridge driver:
(A) FAN8380 which provides internally fixed 100nsec dead-time and is suitable for the ballast and low frequency PWM based half-bridge control, and (B) FAN7382 whose current driving capability is 350mA/650mA (sourcing/sinking current) is a general purpose high/low-side gate driver IC
The HVIC responses for the applied noise power can be sorted into the following four categories:
(1) Normal Operation: The HVIC is normally controlled by the command as a user intends.
(2) Abnormal Operation: The HVIC skips and misses the input command in a medium noise peak. For a high noise peak, the HVIC output is fixed to the lowest level.
(3) Latch Operation: The HVIC output is fixed to the lowest level and large current flows toward the HVIC. But, if reducing the applied noise power, the HVIC is recovered and works normally.
(4) Destruction: The HVIC is damaged permanently. The HVIC is never recovered; in a worse situation, the package gets cracked or explodes.
As shown in Figure 6, the FAN7380 and FAN7382 show an abnormal operation at high-voltage peak. However, the test vehicles are not destroyed and do not fall into the latch state. This means that the designed of these two devices is very robust for high-energy pulsating noise.
Figure 6. Robustness test results:
(A) Positive Pulse Noise Test, and (B) Negative Pulsating Noise Test.IC
The HVIC design based the new technique presented in this article demonstrates good noise immunity and extended allowable negative VS voltage swing. Furthermore, this effective HVIC process offers a robustness which can overcome even difficult situations.
The HVIC itself is significance because it can replace the bulky pulse transformer using silicon technology. But the more important factor to remember is that a power-system-on-a-package is possible with HVIC because it is built on a cheap familiar silicon wafer. For the success of the power-system-on-a-package such as SPM (Smart Power Module) and IPM (Intelligent Power Module), the high-side and low-side gates driver IC's role is very important and the proposed HVIC offers a workable solution for designers.