Here's a simple synchronous buck regulator circuit (Figure 1) that can provide high performance at a very low cost. This switcher will operate from a 3.3 volt or 5 volt input rail, has an output adjustable from nearly zero to Vin, and can deliver several amps. It has high efficiency, is stable with small ceramic caps, can operate at 100% duty cycle, offers extremely fast transient response, has very low output ripple, and can have a sub-dime size footprint. Because of its cool operation and small footprint it can be placed near a low voltage load.
Figure 1 Simple synchronous buck regulator
The circuit is based on a low cost hysteretic switching controller that was designed to drive a PFET in an asynchronous buck configuration. Synchronous operation is obtained by inserting Q2 in place of a catch diode and selecting Q1 and Q2 to have gate threshold voltages greater than one half of Vin. Synchronous switching means better efficiency at full load. This is especially true when Vout is relatively small compared to Vin since the NFET can have much lower loss than a diode. Lower light load efficiency is the tradeoff.
Chosing FETs with gate threshold voltages less than Vcc/2 should be avoided since this will result in a short period during each switching transition when both FETs are on causing a “shoot-through” current spike. Shoot through current spikes cause noise seen as high frequency ringing at the switch node, switching frequency glitches seen at every node, and increased switching loss.
Switching frequency is adjustable and predictable
The switching frequency, Fsw, of many hysteretic buck regulators is dependent upon the inductor ripple current and output capacitor ESR. Ripple current flowing through the ESR produces a ramping voltage at the loop comparator, FB, forcing a state change each time its threshold voltage is crossed. When relying on ESR, Fsw becomes difficult to control since ESR is a typical specification that varies with time and temperature. One can reduce this variability by using a ceramic capacitor with a separate small series resistor. This can be effective but hysteretic ripple will still be present at Vout and Fsw will still vary if any bypassing load capacitance is added. Ideally, one wants the switcher’s output capacitance to have zero ESR to reduce switching noise and provide better transient response.
The circuit of Figure 1 allows Cout to have zero ESR by using Rs, Cs, and Cff to inject ripple into the loop comparator. Then Fsw is dependent primarily on Vin, Rs, and Cff. Cout can be one or more 10μF ceramic caps with typical ESR in the 3mΩ range…less when in parallel. This ESR is low enough to be ignored so Fsw is determined from the values of Rs, Cff, the fixed 21mv hysteresis voltage of the LM3475, and loop delay time. Cs is just a coupling cap chosen large enough to provide low impedance at the switching frequency relative to Rs. Loop delay time is approximately 90ns for the LM3475 + 20ns for small FETs. Switching frequency can be approximated by:
Fsw = D*(1-D)*(Vin-Vout) / (Cff*Vhyst*Rs*(1-D)+Tdelay*(Vin-Vout)); where D = duty cycle, and Rs < (2*vin-1)*rt*rb/(rt+rb)="">
Note that the equation does not include L, Cout, ESRcout, or Iout.
Output voltage limits approach Vin and zero
The internal comparator at the FB pin trips when the voltage reaches 0.8V falling and (0.8V + Vhyst) rising so its center point is (0.8V + Vhyst/2). This leads to the following expression for Vout:
Vout = (0.8+Vhyst/2)*(1+Rt/Rb)-Vg*Rt/Rb; where Vg = 0 for Vout >0.8V. In the rare instance where Vout must be set < 0.8v,="" one="" needs="" to="" provide="" vg=""> 0. A stable Vin can be used for Vg in some applications.
Required design inputs
One must provide these inputs(units) to begin a design:
Vin(V); input voltage in the 2.7V-5.5V range,
Vout(V); desired output voltage, can be lower than Vref if Vg>Vref is supplied,
Vref(V); internal Vref of the device, 0.8V,
Vg(V); voltage supplied to the bottom of Rb, this is zero for Vout>Vref=0.8V,
Vhyst(V); hysteresis voltage from the device datasheet, 0.021V,
Tdelay(ns); prop delay from FB to Dr plus delay from Dr to the switch node, about 110ns,
Ioutmax(amp); maximum desired output current,
Vripplemax(mv); maximum peak to peak output ripple voltage allowed,
Fsw(kHz); choose a switching frequency -- lower for efficiency and higher to reduce size. A circuit with low cost, small footprint, and good efficiency will have Fsw in the 200kHz-800kHz range.