Continuous time delta-sigma (CTΔΣ) analog-to-digital conversion technology shatters the conventional wisdom that pipeline A/D converters are the only conversion technique available for high-speed, high dynamic range applications. CTΔΣ technology offers lower power operation, better dynamic performance, economy of design and specific functional benefits.
In short, CTΔΣ technology means:
1. An inherently power-efficient architecture that eliminates power-hungry sample-and-hold amplifiers (SHA) and the wide-bandwidth gain stages essential to the pipeline A/D converter concept.
2. An alias-free Nyquist sample range is made available by exploiting inherent over-sampling and on-chip digital filtering. Digital filtering permits tailoring of group delay performance and the signal transfer function to specific applications.
3. Simplicity of application through the integration of a clock and low jitter PLL, the elimination of anti-aliasing filters and the integration of input gain stages to simplify input signal path design of high-resolution data conversion systems.
4. Switchless design future-proofs CTΔΣ technology, through its easy migration to the next generation of CMOS processes, enabling the speed and power benefits of the process roadmap to be attained.
CTΔΣ architecture supports high-resolution analog-to-digital conversion systems from 10 to 16-bit and beyond with sampling rates up to 100 MHz.
Today, most A/D converter design work aims to reduce power, particularly in high-speed conversion, and to minimize the number of comparators needed. It is broadly assumed that the pipeline converter provides the highest sample rates whilst yielding high dynamic range. It is used as a standard in data conversion applications at 10-bit and higher resolutions and for sample rates from 5 MHz to 100 MHz or more. The architecture reduces the number of comparators needed by deploying multiple low-resolution flash conversion stages cascaded together to form the pipe. Although the resolution of each conversion stage is reduced, saving on comparators, the first stage must be designed with linearity at least as good as the maximum resolution of the A/D converter (12-bit linearity for a 12-bit A/D converter). Different pipeline implementations exist, but all work by reducing a multi-bit conversion into several lower resolution “flashes” that are processed synchronously. At each stage in the pipe, a reconstruction of the previous stage’s quantized output, generated by a D/A converter, is subtracted from the original input signal. The residual signal is then amplified prior to moving onto the following stage for finer quantization. In pipeline conversion a sample-and-hold amplifier (SHA) is need to acquire the input signal and hold it to better than 0.5 LSB for the duration of the conversion. Once all sub-stages have a valid conversion result, a digital correction block constructs the final multi-bit result.
The pipeline A/D converter is capable of high dynamic performance. However, beyond 12-bits resolution, as the sampled signal moves through the pipeline, transferring the charge associated with a given signal demands high gain bandwidth to ensure stage settling times fall within the limits set by the high frequency signals that are being sampled. To maintain linearity you need to calibrate and correct for the limits in component matching achievable with current process technologies and it is tough to migrate designs from one process to another. As operating voltages fall from one process generation to the next, the input signal headroom is compressed. Furthermore, designing switches with greatly reduced threshold voltages that work well in deep sub-micron processes gets harder.
It’s worth remembering that pipeline A/D converters form only part of a data conversion system, you need in addition to find a low jitter clock source and design input stages that include anti-alias filters. In anti-alias filter (AAF) design, steep attenuation characteristics are hard to achieve, tempting you to consider over-sampling the signal of interest. Over-sampling stretches the Nyquist zone, lowering demands on filter roll-off but the trade-offs are increased system power and higher processing speeds demanded of the back-end DSP system. With continuous time delta-sigma conversion, on the other hand, you don’t need an AAF.