The effective power and supply integrity management for nanoprocessors and other ultra large scale integration designs (ULSI) is well documented. Yield loss and timing problems undetected by traditional verification and validation methods can be traced to a significant decrease in supply noise margin in components using advanced fabrication processes at and below the 90nm node. A combination of increased current density at lower supply voltages and supply pathway impedance results in large, on- and off-chip, supply variations called voltage droops in the literature . These fluctuations make it more difficult to reduce static and dynamic power consumption by further reductions in supply voltage, despite the scaling direction for semiconductors. Simultaneously, finer dimension nanometer processes (90nm and below) exhibit very substantial device variances during manufacturing, necessitating a greater allocation of the design margin to such variations. Therefore, the traditional process-voltage-temperature (PVT) validation methodology (that provided as much as 10% variance to supply voltage in the past) is now moving rapidly toward more stringent supply voltage control and less tolerance of voltage variance. This trend requires that the combination of DC (static) and AC (dynamic) noise on-chip be contained within a narrower supply variance band of 5% or lower in chips in the Nanotechnology era (100nm to 1nm).
Traditional techniques to minimize supply noise such as voltage positioning and on-chip decoupling capacitor integration are becoming increasingly inapplicable in addressing power integrity needs. A voltage regulator module is far too distant, both physically and electrically, to match the power supply bandwidth requirement of gigahertz processors for which the voltage positioning technique is usually employed. Due to the exponential rise of gate leakage in sub 100nm processes, on-chip decoupling is an unacceptable choice for dynamic noise mitigation. The energy stored in these integrated capacitors diminishes quadratically with supply voltage. Additionally, it has been shown in the industry that the scaling of package filter component characteristics, such as the loop inductance of on-package capacitors, and the series resistance of the power path, will be exponential [1, Power Delivery section]. In this article, the techniques of active noise regulation (ANR) and active VLSI packaging (AVP) are introduced. These methods take advantage of proximity to the load component and the quadratic increase in capacitive stored energy with voltage to place stable charge reservoirs where they are most needed -- very close to the high current density and high-speed, transient loads.
A key requirement that ensures the effectiveness of this technology is a rigorous understanding of dynamic noise behavior in a high-performance ULSI component power grid. Tools analyzing the full stack of multiple on-chip power grids, distributed loads, leakage, and decoupling capacitance, that also include the package grid, external connectivity and on-package components are critical for this understanding. Such tools give the designer the ability to visualize the spatial and temporal variation of noise throughout the system, providing a detailed view of the interaction of on-chip dynamic noise with critical path activity. In addition, these tools provide a dynamic view of the noise minimization impact of ANR and other on-package active/passive components. They provide the means to carefully design the placement and temporal activation of ANR's, passive decoupling caps and other components in single or multi-chip systems. True dynamic noise analysis requires the ability to model all key elements of a power grid including power loop inductance for all segments of the power grid, on and off chip standing wave resonances and resistive energy loss. The authors have made extensive use of such a tool, PowerESL, developed for this rigorous analysis of dynamic noise in high-performance systems.