# Cloaking the non-idealities of DC-DC converter stability

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In the world of battery-powered electronics, total chip integration translates to compact, flexible, and low cost solutions, in other words, the ideal products. Power supply circuits, unfortunately, present difficult integration challenges in the form of power density and delivery, which result in the use of large and bulky external power components. What is more, the design values of the power passives and their relevant parasitic components, like equivalent series resistance (ESR) and equivalent series inductance (ESL), vary significantly from one application to the next, on top of their process-, temperature-, frequency-, and drift-over-time dependencies. Ensuring the system is stable over such a wide range of L-C-ESR values is difficult, and in many cases, next to impossible. Switching power supplies are therefore relatively slow and only stable for a narrow band of applications and LC components.

** Masking ESR variance **

The effect of the output capacitor’s ESR on the frequency response of a switching DC-DC converter supply circuit is a left-hand plane (LHP) zero anywhere from moderate to high frequencies, depending on its value, which in turn depends on manufacturer, temperature, and drift performance. Consequently, a designer can neither depend on its existence to maximize phase-margin performance or allow the regulator’s bandwidth to reach those frequencies because the zero would otherwise extend the unity-gain frequency (UGF) to regions where parasitic poles exist, compromising the overall stability of the system.

One way to circumvent these ESR design constraints, however, is to mask the zero by bypassing the output capacitor at moderate frequencies with a feed-forward path [1], as illustrated in Fig. 1 [2]. At low frequencies, C_{1}-R_{F} bypass filter is high impedance and therefore “transparent,” yielding a typical L-C-ESR frequency response. As frequencies increase, however, before the onset of the ESR zero, C1 shorts and feeds more of the ac signal directly to C_{F}, bypassing output capacitor C and its ESR zero in the process. As a result, the L-C-ESR path is high impedance near the vicinity of the ESR zero, having little to no impact on the overall frequency response of the circuit beyond this point; in other words, the bandwidth and phase-margin response of the system are independent of the ESR zero.

*Figure 1. Sample embodiment of a masking feed-forward path (C1-RF)*

The net result of the feed-forward path is the addition of a predictable and relatively low frequency LHP zero. The feed-forward path, in essence, has lower gain than the LC path at lower frequencies and higher gain at higher frequencies, as illustrated by the relative placement of the light solid (main path) and dashed (bypass path) traces of Fig. 2. Since the Y-axis of the Bode plot is in dB, the path with the higher gain determines the combined frequency response of the overall circuit, as shown by the solid dark trace of Fig. 2. At the frequency where the gains of the main and feed-forward paths cross, an ESR-independent LHP zero consequently appears (z_{FF}). The main drawback to this technique is increased output impedance at high frequencies, where the output voltage is masked from the circuit, which translates to slower response times to fast load-dump events.

*Fig. 2. Bode-plot response of the masking feed-forward path*