The demand for precision is relentless, from 0.1% voltage references and 0.5μV offset operational amplifiers to 190MS/second 14-bit analog-to-digital (A/D converter) converters, yet fundamental error sources like transistor mismatch errors over process and temperature and RMS switching noise effects continue to plague performance. Shrinking supply voltages, budget-constrained test times, and rising bandwidth requirements only exacerbate the problem. State-of-the-art analog circuit solutions therefore succumb to trimming or switching networks to mitigate these process-induced errors. Unfortunately, neither of these techniques is especially attractive to the designer because trimming is costly and switching is noisy, which is why alternate circuit solutions are desired.
Trimming is a post-fabrication circuit adjustment aimed at correcting the process-induced offsets of various components. The temperature-drift dependence of this adjustment should track that of the offset. Typically, one or more strategically placed resistors are tuned to offset the mismatch errors of two or more devices.
The resistance is varied by:
(1) fabricating a number of binarily weighted resistors and open- and/or short-circuiting them with on-chip fuses or
(2) reshaping and therefore resizing a resistor with a laser .
The accuracy of the former is limited by the reach and resolution of the trim resistors, that is to say, the initial mismatch accuracy performance that sets the full-scale trim-range resistance and the silicon area and test-time boundaries that limit the total number of bits that can be afforded. Laser trimming, on the other hand, is more accurate and area efficient and therefore often used in high performance data converter applications, but its inherent cost in test time and equipment is many times prohibitive.
The reason why trimming in general is so attractive is that many process-induced errors have an almost linear temperature dependence, like several of the mismatch and offset errors in a bandgap reference  and a bipolar differential pair, and consequently trimming at one temperature, for instance, room temperature is sufficient to cancel the temperature drift of the offset . Its cost in manufacturing time, however, can account for 25% of the total cost of a power management IC , and this is only to correct first-order (linear) errors. The temperature dependence of higher order errors present in bandgap circuits and MOS and BiCMOS amplifiers are not compensated, only their absolute offsets at the trimming temperature (for example, room temperature) are reduced. Compounded to this are package stress-induced offset errors because most trimming procedures are performed at wafer level to circumvent the increased costs of post-package EEPROM trimming procedures. Package shift offset effects can be reduced by adding post-fabrication low-stress mechanically compliant layers to the IC before encapsulating it with plastic , but again, adding these compounds is costly.