In the expanding world of portable electronic devices, there is no one single parameter more important than battery life, or more important than efficient power conditioning, which is why switching regulators are so popular. Linear regulators may be simpler and less noisy but their switching counterparts are more efficient and therefore preferred, when possible, and while step-down buck switching converters are more efficient, step-up boost converters are often necessary and unavoidable, especially in battery-powered systems. Many designers are therefore confronted with the challenge of decreasing the power losses of a boost switching regulator, and understanding the basic mechanisms that incur power losses and their associated design tradeoffs is key in this regard. Literature on the subject, unfortunately, tends to concentrate on buck converters , and the results are often involved and with limited circuit insight. The objective of this article is to perhaps unscramble and hopefully bring insight into the power-consuming mechanisms of a boost converter, establishing the means by which a designer can more effectively balance design choices.
A Typical Boost Converter
A DC-DC boosting function is basically realized by first energizing an inductor in one cycle and releasing the stored energy to the output in the other, as realized by the circuit shown in Figure 1a when switch MN is engaged (MP and D are off) and inductor L is energized (connected from input supply VIN to ground) and later when switches MP and D are on (MN is off) and the energy stored in L is released to the load and output capacitor in the form of a current. Since the average voltage across the inductor in steady state is zero, the average voltage at the switching phase node VPH is equal to VIN and its peak voltage (VPK) is therefore higher than VIN, the latter of which is impressed across output capacitor C via peak detector switch combination MP-D (VOUT ≈ VPK). The on time of the circuit is defined as the time interval for which MN conducts and inductor current rises, as shown in Figure 1b, and off time alludes to the time when MP-D conduct a decreasing inductor current. Broadly, three basic mechanisms incur power losses in the boost switching converter: conduction losses resulting from switch-on and series parasitic resistances (I2R), switching losses resulting from current-voltage overlapping events across the switching transistors (when switching node VPH is neither at ground nor VOUT), and gate-drive losses, which amount to the energy required to charge and discharge the gate capacitances of the switching transistors.
Figure 1a Simplified circuit schematic
Figure 1b Switching waveforms of a switching boost converter