Increasing usage of battery-powered portable (often wireless) electronics systems is driving the demand for complex system-on-chip (SoC) that consume the smallest possible amounts of power and area and provide increased functionality and performance. Meeting all these requirements is a considerable design challenge, especially in designs targeted to 65-nanometer and finer process geometries. In these process geometries power-related constraints are imposed throughout the flow in order to maximize device performance and reliability.
What designers need is a power-aware design flow that allows them to make timing-versus-power and area-versus-power at different stages of the design flow. In order to achieve this, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with - and applied throughout - the entire RTL-to-GDSII flow.
In addition, designers need an advanced multiple voltage domain (multi-Vdd) methodology that includes MTCMOS switch insertion and automatic level shifter/isolation cell insertion. Multi-Vdd architectures vary the voltages in different regions of the design, allowing designers to implement large, complex SoCs that consume less power. Multi-threshold CMOS (MTCMOS) switches allow blocks to be turned on or shut down depending on the mode of operation.
This article describes key power considerations and how they can be addressed using an advanced, virtually flat multi-Vdd methodology.
Figure 1: Types of Multi Vdd Designs