As the personal computer industry pushes towards core voltage of 1 volt at 200 amps great pressures are placed on the semiconductor industry to meet those requirements and provide the methodology to tailor make new devices for this market. Historically, MOSFET designers responded to the market demands by doing incremental improvements in performance that were generally satisfactory. Now, they are facing the need for a radical departure from reactive to proactive design approach that should allow them to serve the ever increasing need for higher currents, higher efficiency and smaller footprint that suits the ever shrinking real estate allocated to DC-DC converters. One such approach, proposed here, is to design MOSFETs that targets this market with surgical precision. This, radical change is justified since the market is large enough to justify the needed expenditures and provides for a very responsive solutions for the market needs.
Figure 1. Buck Converter
MOSFETs design approach:
The synchronous buck converter is the topology of choice for DC-DC converters for the PC market and is widely used in the telecommunications market among others. We will consider only this topology in this paper but the same methodology may be applied for other topologies too. We shall attempt to derive an equation for the optimum MOSFET die size based on two factors
- It's position in the circuit that is, the power switching MOSFET or the synchronous rectifier
- The total losses associated with this particular MOSFET.
The choice of the total losses as a determining factor directly relates to the demand of the industry for higher efficiency and hence lowers losses. The optimum die size is that which provides the least amount of losses when a MOSFET of that optimum die size is used in the position it was intended for, that is, switching MOSFET or synchronous rectifier. It is clear that such an equation depends on the particular process that is used to fabricate the device and the particular device design using this process. By tying the device size to the physical application parameters we can examine the different influences of these parameters on the device and best of all we can design one that is finely tuned to the demands of the application or in other words an Application Specific MOSFET. This approach should enable the power semiconductor industry to produce power devices that will meet the requirements every time and eliminate the guess work from the design process resulting in a shorter and less expensive development cycle.
In order to simplify the resulting equations we have limited the calculations of the losses to the two predominant sources of losses:
- Conduction Losses and
- Dynamic or switching losses.
The losses that have been ignored are charge-discharge losses of the Gate-to-Source capacitance and the Drain-to-Source capacitance. These two sources of loss represent a small percentage of the total losses per device given a switching frequency of 300 KHz and input voltage of 12 Volt. On the other hand, though including these two sources does complicate the mathematical derivation using Maple, it makes the resulting equation too complicated to study the effects of the application parameters on the device size