For more than three decades bulk-silicon MOSFET has been the transistor workhorse of CMOS technology. We have become terribly addicted to the density and performance gain from shrinking it. More speed, more memory for the same cost (almost), is so wonderful! Incremental process improvements have so far enabled smooth feature-size scaling to the 90nm technology node. However, the need to maintain leakage and performance at deep nanometer dimensions is rapidly painting the classical transistor into a tight corner. To continue scaling the performance, new materials and structures are making their way into the classical CMOS. Facing unprecedented power-performance challenges at 32nm and beyond, will the transistor evolve rapidly through a succession of leaping innovations? Although the answer is still in the making, evidence of new material and device structures ranging from metal/High-K gate stacks, novel strained silicon to multiple-gate devices are vying to initiate the revolution.
Packing transistors to achieve density doesn't come free, tiny transistor dissipate energy when they are busy switching. This energy penalty to process information is measured by the dynamic power:
Dynamic Power = CVdd2F
C= Device Capacitance
Vdd = Supply Voltage
F = switching frequency
Moreover, being imperfect switches, they leak even when they are supposed to be turned off, contributing to the standby power dissipation.
Standby Power = Ileakage X Vdd
Ileakage = leakage current
The dissipated power adds up quickly when you cramp 100's of million of them into a die area of 100 mm2, and it is just going to get worse. Managing power is now a pre-dominant activity for the entire crew from systems, design to process. Dropping power consumption is not hard (you can always shut things down) until you have to balance it with performance.
In our haste to shrink the gate and channel, source/drain junctions and gate dielectric scaling were not able to catch up, due to process and material limitations. This led to poorer short channel electrostatics and weaker gate influence over source-to-drain leakage when the device is supposed to be turned off (that is, sub-threshold mode). The increased sharing of the channel charges between the gate and the encroaching source/drain (Figure 1), leads to an increase in sub-threshold leakage, reflected by the undesired reduction in threshold voltage (Figure 2).
Figure 1. Illustrations showing the effects of charge sharing for a device with (a) uniform channel doping, (b) ultra-shallow junctions, and (c) High pocket implant doping
Figure 2. A plot of device threshold voltage (VT) and source/drain leakage as a function of gate length (Lg). The onset of short-channel effects causes VT to reduce for smaller Lg. This is accompanied by an exponential growth of source-drain leakage