While the interleaved DC/DC converter topology, versus the traditional paralleling of output stage transistors, is the way to go for high-efficiency designs, it can be even better. In interleaved operation, a number of mini-converter cells (or phases) are placed in parallel. Ideally, active phase-shifting control circuitry evenly distributes power among the phases, and this approach cancels the current ripple at the output as well as increases the effective ripple frequency, thus reducing the output filter capacitor requirement. The interleaving approach can also significantly reduce input inductor and capacitor requirements.
But there are several drawbacks. For one, there's a tradeoff between the converter's full- and light-load efficiency. With transistor stages in parallel, conduction losses are reduced but switching losses increase. This works well at full-load, because conduction losses dominate. But switching losses take over during light-load conditions. In addition, current sharing between phases become a troublesome issue. Active control generally takes care of this (without it, a tiny component mismatch among the parallel phases will lead to dramatic phase-current imbalance), and some ways are better than others.
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Figure 1: A two-phase interleaved two-switch forward converter.
Digital power management, with its ability to perform sophisticated control algorithms and its databus capabilities, more powerfully addresses these issues. Here we apply the technique to a two-phase interleaved two-switch forward converter to achieve real-time optimization.
A. Light load versus heavy load
In a switching power converter, the total energy loss is the sum of conduction loss, Pcond, and the switching loss Psw. With a given output current, Iout, and switching frequency, fs, the switching loss is (Eq. 1):
Psw = Psw1 + Psw2 = ksw1 · Iout · fs + ksw2 · fs
where ksw1 and ksw2 are the switching loss coefficients related to the components. As a general rule, with a larger-die transistor, ksw1 and ksw2 are higher.
Without our considering the inductor current ripple, the conduction loss on the path resistance, Rpath, is (Eq.2):
Pcond = Iout2 · Rpath
Utilizing interleaved phases in parallel can increase the heavy-load efficiency by reducing the path resistance. On the other hand, at light load, the power loss is dominated by the switching loss. With ksw1 and ksw2 increasing with more phases, the interleaving operation significantly drags down the light-load efficiency. Hence, compared with a single phase converter, the interleaved multiphase converter has a higher efficiency at heavy load; there's a penalty at light load. The converter's efficiency is (Eq. 3):
For single-phase converters, the power conversion efficiency is zero at no load, since part of the switching loss, Psw2
, always exists. As the output current increases, the efficiency increases as Psw2
becomes negligible. The denominator in Eq. 3 is a second-order polynomial, while the numerator is only first order, so the efficiency goes down again as the output current passes an optimal point. With a two-phase converter, the output current at the efficiency optimal point is twice that of a single-phase one. As a result, the more phases, the higher the efficiency at heavy load; but at light load, the more phases, the lower the efficiency.
Traditionally, only the full-load efficiency was considered to be important. Today, however, a power converter must supply a light load more often than a heavy load. With continually increasing demand for saving energy, high light-load efficiency is crucial for power supplies. Designers thus look to intelligent interleaving controllers to achieve high efficiency at all loads.
B. Real-time efficiency optimization with phase numbers
The preceding analysis of power loss shows that allowing both parallel phases to operate at light loads is undesirable. With one phase turned off, however, we gain an advantage. The conducting losses increase, but the switching losses are reduced, and thus there is higher efficiency at light load. The key is to secure real-time optimization of the number of phases.
Figure 2 illustrates the experimental waveforms for a two-phase interleaved two-switch forward converter, in this case controlled by Analog Devices' ADP1043 digital controller. When the total load current drops below a certain threshold, the second phase is disabled. As shown in Figure 3, with one phase shut down, the light-load efficiency is improved. The difference in light-load efficiency with or without phase optimization control can be as much as 15 percent.
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Figure 2: Automatic phase shutdown with the ADP1043.
C. Real-time efficiency optimization with DCM operation
As we see from Figure 3, the efficiency drops dramatically with extreme light loads even in single-phase operation. One of the reasons is that synchronous rectifiers are utilized in the secondary side of the converter (Fig. 1). When the output current level is lower than the current ripple, reverse current flows through the output inductors. As a result, conduction losses occur due to circulating currents. One solution to improve the efficiency is to shut down all the secondary synchronous rectifiers, and to rely on the body diodes or paralleled diodes (Schottky diodes in most cases) for freewheeling. When the load is sufficiently low, the converter will operate in the discontinuous current mode (DCM), avoiding the issue with circulating currents.
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Figure 3: Efficiency, interleaved two-switch forward converter.
With this scheme, the efficiency will increase by 5 percent as compared to continuous current mode (CCM) operation. And shutting down one phase at light load further boosts efficiency over the application load range.
D. Other considerations
Beyond these steps to optimize real-time efficiency, the designer must look more closely at the power stage and controller design. There are inherent propagation delays in the power stage, sensing network, and feedback control circuitry, and so in phase 1 the system must maintain output-voltage regulation before the circuitry turns on the second phase during fast load step-up transients; the system should also be able to handle full power for a short time. The transistors should be selected based on this thermally sensitive condition. In addition, the magnetics should be designed to avoid saturation for a higher output current.
As for the controller, the feedback compensators need to be modified for different operation, because the power stage transfer functions vary with the phase number and CCM/DCM conditions. This function requires smart management from the controller. It's very hard to do with a traditional controller. On the other hand, digital power management controllers are able to automatically detect the load condition and smoothly switch to the appropriate converter mode.
Current sharing between phases
Interleaved operation by itself does not ensure the currents are well shared. Since the paralleled phases share the same voltage feedback, no error exists as a result of reference mismatch. Thus the load imbalance is a function of component tolerances, drive imbalance, and timing errors.
Current imbalance results in thermal and device stresses. The transistors and magnetic components have to be overdesigned for the possibility of overstresses. In addition, the efficiency suffers. For example, if the total current in an interleaved forward converter is 30 amps and the two phases supply 10 amps, and 20 amps, respectively, the drop in efficiency due to that factor is almost 1 percent.
Two control schemes are used to achieve current sharing among phases: inner loop current sharing, and dual-loop current sharing. Inner loop current sharing is inherently current-mode control. The output of the voltage compensator serves as the current sharing bus and provides the output current reference for all phases. Inside the voltage loop, the current sharing loop design is not limited by the voltage bandwidth. The current sharing response can be even faster than the voltage loop. When designing the outer voltage loop, however, the influence from the inner loop must be included. A faster inner loop might degrade the outer loop's voltage regulation function.
In dual-loop operation, on the other hand, the voltage regulation loop and current sharing loop are in parallel. Each phase has a dedicated current sharing compensator to ensure that its current follows the current sharing bus, which could be the average current of the paralleled phases or the highest phase current. The output of each phase's current sharing loop is added to the common voltage compensator output to generate the duty-cycle signal for this phase. In this way, both the current sharing controller and the voltage regulation controller influence the generation of the duty-cycle signal. This control structure enables flexible design of each loop and the designer need not be overly concerned with interaction between the current sharing and voltage regulation loops.
For both current sharing schemes, each phase's current must be sensed for active control. A traditional solution is to employ a current-sense scheme for each phase. Current sensing is generally used for protection purposes. This technique adds a bit of cost to the interleaved converter.
To sense currents from two phases with a single input, the controller has to separate the current for each phase. In the interleaved forward case, the main switch duty cycle is always less than 50 percent to avoid transformer saturation. With 180 degrees phase shift, there is no signal overlapping with the main switch current sensing. Thus, with digital control, the sensed signal can be distributed to align with the duty cycle signals for each phase. In this way, each phase's current can be well identified using only one current sensing circuit. The controller monitors the currents flowing in both phases, stores this information, and compensates the drive signals to ensure equal current.
Figure 4 illustrates an example of an interleaved forward converter that implements the above scheme using an ADP1043 controller. Clearly, with a common current sensing point, the controller is able to identify the current for phases since the duty cycles are less than 50 percent. Without the current sharing control, the second phase's current is almost twice of that of the first phase. With current sharing control enabled, the difference between the phase currents is significantly reduced, to 5 percent.
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Figure 4. Effectiveness of the current sharing control between phases: (top) With current sharing control; (bottom) without current sharing control.
In summary, interleaved operation provides benefits that single-phase designs lack. Using digital power management can further extend the benefits of interleaved operation. Digital control also provides a simple scheme for current balancing.
About the author
Yang Qiu (firstname.lastname@example.org) is a senior applications engineer with Analog Devices Inc., San Jose, CA. He received his B.S. and M.S. degrees in electrical engineering from Tsinghua University, Beijing, China, and a Ph.D. from the Center for Power Electronics Systems (CPES), Virginia Tech, Blacksburg, VA.