(Editor's Note: To see a linked list of all entries in this series, click here.)
A noise-free power supply is not an accident. A good power supply layout in particular is essential to minimize lab time when bringing up a new design. A few hours or even minutes spent looking over the layout can save days of troubleshooting down the road.
Figure 1 shows a block diagram of some main noise-sensitive circuits within a power supply. Here the output voltage is compared against a reference to generate an error signal. The error signal is compared to a ramp to generate a PWM signal that is used to drive the power stage.
Noise can be injected in three major areas: error amplifier input and output, reference, and ramp. Careful electrical and physical design of these nodes can help minimize checkout time. Generally, noise is capacitively coupled into these low-level circuits. A good design makes sure that the low-level circuits are compactly routed away from any switching waveforms. Ground layers can provide shielding also.
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Figure 1: Low-level control circuits offer ample noise opportunities
The input to the error amplifier is probably the most sensitive node in the power supply as it usually has the most components connected to it. Combine this with the stage's very high gain and high impedance, and you have a recipe for disaster. During the layout process, you must minimize the node length. You need to place feedback and input components as close as physically possible to the error amplifier. If there is a high-frequency integrating capacitor in the feedback network, you should place it close to the amplifier, followed by the other feedback components. Also, the compensation networks may be formed with series resistor-capacitors. For best results, place the resistor toward the error amplifier input so that if a high-frequency signal gets injected into the resistor-capacitor node, it has to work against the high resistor impedanceórather than the capacitor.
The ramp is another potential noise problem area. Ramps are usually generated by either charging a capacitor (voltage mode), or derived from a sample of the power switch current (current-mode). Usually voltage-mode ramps are not an issue in that the capacitor presents a low impedance to high-frequency injected signals. The current ramps are much more problematic due to leading-edge spikes, relatively small ramp amplitudes, and parasitics in the power stage.
Figure 2 shows some of the issues with current ramps. The first trace shows the leading edge spike and the following current ramp. The comparator (depending on its speed) has two potential trip points. The result is chaotic control operation, which sounds much like bacon frying.
This problem is best fixed with leading-edge blanking in the control IC, which ignores the very first part of the current waveform. High-frequency filtering of the waveform also helps. Again, place the capacitor as close as physically possible to the control IC. Another common problem is subharmonic oscillation, as illustrated in both waveforms. This wide-narrow drive waveform is indicative of inadequate slope compensation. Adding more voltage ramp to the current ramp will fix this problem.
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Figure 2: Two common current-mode noise issues
You've been really careful with your layout. But your prototype is still noisy. What do you do now? First verify your loop response to eliminate instability as the problem. Interestingly, a noise problem may appear to be an instability at the crossover frequency of the power supply. But what's really happening is that the loop is correcting out an injected error as fast as it can respond. Again, the best way to proceed is to recognize that the noise is being injected in one of three areas: error amplifier, reference, or ramp. You simply need to divide and conquer!
The first step is to probe the nodes. See if there is an obvious nonlinearity in the ramp, or a high frequency variation in the error amp output. If you cannot detect anything, take the error amplifier out of the circuit and replace it with a clean voltage source. You should be able to vary the output of the voltage source to smoothly vary the power supply output. If this works, you have narrowed the problem to the reference and error amp.
Sometimes the reference in a control IC is susceptible to switching waveforms, and this condition may be improved with additional (or proper) bypassing. Additionally, slowing the switching waveforms with gate-drive resistors may help. If the problem is the error amplifier, often lowering the impedance of compensation components helps as this reduces the amplitude of the injected signal. If all else fails, remove the error amplifier nodes from the printed circuit board. Air wiring the compensation components can help to identify where the problem is.
Next time, we'll address the first part of two in damping an input filter.
For more information about power solutions, visit www.power.ti.com . If you have any questions about the material in this article, I can be reached at firstname.lastname@example.org.
Robert Kollman is a Senior Applications Manager and Distinguished Member of Technical Staff at Texas Instruments. He has more than 30 years of experience in the power electronics business and has designed magnetics for power electronics ranging from sub-watt to sub-megawatt with operating frequencies into the megahertz range. Robert earned a BSEE from Texas A&M University, and a MSEE from Southern Methodist University.
To further add to Sreeram's comments, if the switching frequency and A/D frequencies beat frequency caused by even sub-harmonic synchronization, if the beat frequency is known by the uP then these samples can be weighted more or given priority in noise elimination alogrithims because those samples that can be ensured to be within a constant state (On or off period depending on topology)will not have switching transent noise present.