(Editor's Note: To see a linked list of all entries in this series, click here.)
To see a video on this topic by the author, click here.
(April 2011: We've updated this Power Tip to include a video by the author; you can see it at the bottom)
Here is a short collection of power-supply error-amplifier pitfalls that you can easily avoid. They include improperly calculating the gain of the error amplifier, asking the amplifier to do something it can't, and improperly laying the circuit out. Figure 1 shows a typical power supply utilizing a control IC with a built in error amplifier.
Figure 1: The error amplifier is built into the control IC.
(Click on image to enlarge)
The amplifier positive input is connected to an internal reference, the negative input is brought out through the FB pin, and the output is brought out through the COMP pin. The power supply output voltage is set by the voltage divider R5 and R7.
The first common error amplifier mistake is using R5 in the AC small signal gain calculation, when it actually has no impact. If the error amplifier is treated ideally, its inputs are a virtual ground. This means that no AC current will flow through R5, and there will be no impact on the AC small signal gain. You can easily convince yourself by taking a Thevenin equivalent circuit looking from the error amplifier toward the input. (See the appendix, below.)
The second common mistake is to ask the amplifier for more gain than it is capable of providing. Figure 2 illustrates this point. It shows a desired error amplifier frequency response, the gain of the amplifier, and the predicted performance given the limitations of the error amplifier.
Figure 2: Error amplifier bandwidth limits available gain.
(Click on image to enlarge)
The amplifier can not give the desired high-frequency gain due to its bandwidth limitations. Although not shown, the phase is also severely compromised. This is particularly a problem in voltage mode converters (like Figure 1) where a large gain at high frequency is desired. When designing the error amplifier compensation, pay particular attention to its bandwidth limitations, or you may end up with an oscillating power supply.
The most serious parasitic capacitance issue usually involves routing the feedback (FB) voltage and compensation nodes of the error amplifier. This is due to the high impedance of the error amplifier input, the high of gain in the error amplifier, and the large number of components connected to this node.
Figure 1 shows this trouble spot in a typical controller and one of the more likely coupling nodes. The connection between Q1 and D1 has very high slew rates in the order of 0.1 V/ns to 1 V/ns, and can create 1 mA of current with only 1 pF of parasitic capacitance.
Typically, the impedance on the FB and compensation nodes are on the order of 1 kO to 10 kO so this current can create significant voltage perturbations on the error amplifier input. This is usually manifested as erratic gate drives or a perceived oscillation as the power supply tries to correct for the error injected from the noise source.
The most successful designs will recognize this fact and draw the schematic so that the compensation components are shown in the vicinity of the error amplifier; implying a recommended routing. Make sure that the components are compactly placed near the error amp and that the traces that connect them are short. Also, make sure that there is not a high dV/dt trace in the vicinity of these components. This includes the switch node and gate drive signal.
Another common problem is not using proper impedances in the feedback circuit. The error amplifier has a limited drive capability and has to develop suitable voltages across the feedback components. In the case of Figure 1, the drive capability of the error amplifier is only 100 µA and it must develop voltages on the order of a volt. Impedances connected to the output of the error amplifier or in its feedback loop should not be less than 10 kO.
Be careful to not use too large of impedance values in the feedback loop, as this increases the susceptibility to picking up noise from switching waveforms. Figure 1 also shows the best way to configure the feedback components around the error amplifier. Resistors are connected to the high impedance error amplifier input (FB) rather than capacitors. This reduces the noise susceptibility of the R6/C9 and R4/C3 nodes by making them effectively low impedance. The other sides of the capacitors connect to a low impedance point in the circuit and reduce the potential for noise coupling.
To summarize, there are many opportunities for making mistakes with an error amplifier. They include improperly calculating the gain of the error amplifier, asking the amplifier for more gain than it can provide, and improperly routing the circuit. A little attention to these points can help avoid hours in the lab debugging your circuit.
Please join us next month when we will discuss more about feedback loop basics in a DC/DC converter.
Error amplifier gain with voltage setting resistors:
Figure 3. Taking a Thevinen equivalent circuit from the error amplifier input.
(Click on image to enlarge)
(Click on equations to enlarge)
About the author
Robert Kollman is a Senior Applications Manager and Distinguished Member of Technical Staff at Texas Instruments. He has more than 30 years of experience in the power electronics business and has designed magnetics for power electronics ranging from sub-watt to sub-megawatt with operating frequencies into the megahertz range. Robert earned a BSEE from Texas A&M University, and a MSEE from Southern Methodist University.
At last, the problem of the error amplifier driving capability was spoken out. I encountered this issue when using the TL5001 converter IC. The application note recommended the feedback loop components values, which were unacceptable for the design and the impedances were to increase by the factor of 20.
If the load capability of an error amplifier is violated a start-up overshoot and undershoot are to be anticipated. This may deteriorate the power supply and its load viability. The TI app engineers I had spoken to agreed on that but the application note for the TL5001 has not been corrected yet.
It is very important to obtain the expression for the feedback loop with the assumption of the finite bandwidth of the error amplifier, which would allow for formalizing the design process. Something has been done by the author of these lines but the expression comes out to be very complicated. Those who are interested in may try on their own.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.