This article addresses the challenges of designing a 1.5-V 2.4-GHz CMOS Phase Locked Loop (PLL) for wireless LAN applications and begins with the VCO because it is one of the most important elements in the PLL system.
The schematic of the VCO is shown in Figure 1. Transistors M8 and M9 form a NMOS cross-coupled differential pair to provide the negative resistance, which is required for generating an oscillation. M0, M1 and R3 form the biasing network for the oscillator. L7 and C8 form the filtering network to suppress the high frequency noise generated by the bias current source.
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Figure 1. Schematic of the VCO.
Design of the filtered biasing network
Choosing the appropriate bias current and transistor sizing are the two critical factors in the design of a low-phase-noise VCO.
In Figure 1, a VCO core current (i.e. ID of M1) of 4.5 mA is chosen. Simulations show that further increasing the core current (i.e. greater than 4.5 mA) will only provide trivial improvement of phase noise performance. The sizes of the two biasing transistors are chosen to be 25 micron/1 micron (M0) and 200 micron/1 micron (M1), respectively. The resistance value of R3 is equal to 1 kilo ohms.
To further reduce high-frequency noise in the biasing network, we make use of a filtering technique to suppress the contribution of the noise component around 2 fCenter to the overall phase noise, where fCenter stands for the center frequency.
An LC network formed by L7 and C8 are used to accomplish the task. Note that L7 and C8 together compose of a low-pass filter, which suppresses the noise around 2fCenter by sending the high-frequency noise from the drain terminal of M1 to ground. The inductance value of L7 is equal to 1.35 nH and the capacitance value of C8 is 23 pF.
MOS varactor design
The characteristics of MOS varactors directly affect the sensitivity performance of the VCO. In this design, each MOS varactor is built of a NMOS transistor whose drain and source terminals are connected together. The simulated capacitance versus Vg curve of a 500 micron/1 micron NMOS transistor in the presence of a 1.5-V Vg is shown in Figure 2. As we can see, the capacitance value ranges from 0.9 pF to 2.6 pF, with the center control voltage being positioned at about 0.75 V.
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Figure 2. Capacitance vs. curve of a NMOS transistor ( = 1.5 V).
The relationship between the control voltage and VCO output frequency is listed in Table 1. This indicates that the gain of the VCO KVCO is approximately equal to 937.5 MHz/V.
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Table1. Control voltage vs. VCO frequency
The phase noise performance of the VCO is shown in Figure 3. The phase noise's RMS value is approximately equal to - 103.8 dBc/Hz at 100 kHZ:
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Figure 3. Simulated phase noise of the VCO around 2.4 GHz.
Charge pump and loop filter
The schematic of the conventional charge pump and loop filter used in a standard PLL is shown in Figure 4.
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Figure 4. Conventional charge pump and loop filter
In the foregoing schematic, the current sources are designed to minimize the mismatch between the charging and discharging paths (i.e.,Iup = <>Idown). The charge pump current and loop filter components R0, C0 and C1 are designed to achieve a loop bandwidth of 800 kHz and a phase margin of 67 degrees.
Given the loop bandwidth and the maximum phase margin, we can utilize the following equation to determine the design parameters of the charge pump and loop filter,
where KVCO> is the gain of the VCO (in rad/V )and N is the prescaler factor. Also, the expression for the phase margin of the system is given by
By equating the first differential to zero, we can obtain the maximum phase margin, which occurs only if,
The three variables Iup (Idown, C0, and C1 can then be determined by rearranging the preceding equations. The calculation results are shown in Table 2.
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Table 2. Design parameters of the charge pump and loop filter
An improved charge pump circuit that can utilize the foregoing design parameters has been proposed by C.-M. Hung and K. K. O ("A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop," IEEE JSSC, vol. 37, pp. 521-525, April 2002).
The main purpose of this modification as compared to the conventional one is to reduce the current glitches in the charge pump output due to the parasitic capacitances. The redesigned charge pump is shown in Figure 5. In this circuit, the residual charges due to parasitic capacitances are shunted to ground during the switching intervals between "UP" and "DOWN", or "Push" and "Pull" modes.
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Figure 5. Redesigned charge pump based on C.M. Hung and K. K. O proposals.
The most significant advantage of fractional-N architecture over the conventional integer-N architecture is that the resultant output frequency can vary by a fraction of the input frequency. However, the major drawback of the fractional-N structure is that a noticeable amount of quantization noise is introduced into the loop by the quantizer.
It is known that if a constant fractional factor is used, the resulting quantization noise will be toned at a certain signal frequency.
On the other hand, if a randomly changing division ratio is used, the resulting quantization noise will have a spectral characteristic similar to that of a white noise. In the latter case, the delta-sigma modulator is a good candidate to reallocate or to reshape the qunatization noise such that a large portion of the noise power is moved to the high frequency range, which can then be filtered by the low-pass loop filtering and the prescaler's decimating-like operations.
In this design, a third-order single-path (i.e. non-cascaded) delta-sigma modulator with 8-level (i.e. 2.5-bit mid-thread) quantizer similar to the one reported by W. Rhee, B.-S. Song, and A. Ali ("A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order delta sigma modulator, "IEEE JSSC, vol. 35, No. 10, October 2000) is utilized to shape the quantization noise out of the signal band. The generic diagram of the delta-sigma modulator is shown in Figure 6.
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Figure 6. Third-order delta-sigma modulator with an 8-level quantizer.
In Figure 6, X is the desired fractional scaling factor (e.g. 126.5) while Y contains a list of integers (e.g. 134, 132, 130, 128, 126, 124, 122, and 120). These integers or indexes have been inherently noise-shaped by the delta-sigma modulator. They will be sent to the prescaler input.
The generic diagram of a phase/frequency detector (PFD) is shown in Figure 7.
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Figure 7 Phase/frequency detector.
As shown in Figure 7, the detector may highlight either "UP" or "DN", depending on the polarity of the phase difference between fRe f and fdiv. In other words, "UP" will go high when fRe f is ahead of fdiv (i.e. a phase lead); otherwise, "DN" will go high (i.e. a phase lag).
The transient response of the PLL system is shown in Figure 8.
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Figure 8 Transient response of the PLL system.
Ripples in the Vcontrol (control voltage to the VCO) are illustrated in Figure 9.
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Figure 9 Ripples in the Vcontrol.
In this article, the design of a 1.5-V 2.4GHz CMOS phase locked loop implemented in the TSMC 0.35 micron technology has been discussed. The circuit implementations of the VCO, charge pump/loop filter, fractional-N prescaler with delta-sigma modulation and phase/frequency detector have been detailed. A new charge pump/loop filter circuit is implemented and simulated together with the other part of the PLL systems.
About the author
Mingliang Liu is a program manager at Foxlink International, Inc. Prior to this position, he served as a product development manager at Extron Electronics, and a product manager at AV Link. He holds a B.S.E.E. degree from Beijing Institute of Technology and a M.S.E.E. degree from Oregon State University. He can be reached at email@example.com.